Excitation Richness Monitor — System Identification/Validation
System_Identification/Validation/Excitation_Richness_Monitor · 1 input / 2 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Excitation Richness Monitor
System Identification / Validation
Watches whether the data flowing past is rich enough to identify a model with, by accumulating the regressor information matrix and reducing it to two scalars:
S = Σ φφ′, outputs det(S) and trace(S)
It is the missing half of every recursive estimator's warm-up caveat. An estimator reports what it fitted; this reports whether the data supported fitting anything, so a diagram can gate “trust the estimate” on “the data could actually identify it”.
How to read the two outputs. det(S) is the product of the eigenvalues of S, so it collapses toward zero as soon as any direction of the regressor space goes unexcited – which is exactly the condition that makes a parameter unidentifiable. It is not scale-free, though: it grows like the n-th power of the signal amplitude. trace(S) is the sum of the same eigenvalues and supplies that scale, so the quantity worth thresholding is det against a power of trace rather than det alone.
Stateful and discrete by nature: it declares itself discrete-only and always steps at its own rate.
Ports
- phi – the regressor, a column [n, 1]. n is taken from this port, not from any parameter, so nothing can disagree with the signal wired in. The usual source is a Tapped Delay of the input, or the same regressor already feeding a Recursive Least Squares block.
- det – det(S), a scalar. Zero means the data is rank-deficient in at least one direction.
- trace – trace(S), a scalar, always positive once any signal has arrived. The scale to judge det against.
Parameters
- Accumulation Method – how the sum is aged. The two are different
computations, not two tunings of one:
- Forgetting Factor – an exponential tail, S ← λ·S + φφ′. Cheap: the only state is S itself. Responds smoothly, and never fully forgets.
- Sliding Window – a rectangular window of the last N regressors, held in a shift register and evicted exactly. Answers “was the data rich over this stretch” with a definite boundary, at the cost of carrying N×n past values.
- Forgetting Factor (λ) – in (0, 1], used by the first method only. It scales the accumulator every step, so an unexcited direction decays as λk while an excited one settles near 1/(1−λ). Unlike a recursive estimator's forgetting factor, this one cannot wind up: the accumulator is multiplied by λ rather than divided by it, so the recursion is a contraction and λ near 1 is safe here even though it is dangerous in Recursive Least Squares.
- Window Length (N) – a positive whole number, used by the second method only. Until N regressors have arrived the window is still filling, and det is legitimately small – that is the block reporting a real warm-up, not an artefact.
- ⚠ λ and N are bounded by the EXPORT format, not by stability. det is the n-th power of the accumulator's scale, and the scale is roughly 1/(1−λ) or N, so det grows very fast in both. The Q16.16 fixed-point format the three HDL targets use saturates near 32768: measured on a 3-tap regressor of a unit-amplitude signal, λ = 0.997 reaches det ≈ 1.3×106 and overflows, λ = 0.93 peaks near 287, and a window of N = 32 near 3400. Software targets carry the full double range and are unaffected. If a model is destined for HDL, choose λ and N so that (scale)n stays inside the format, or read the block's trace output instead, which grows only linearly.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets, and the three HDL targets are genuinely synthesizable
Q16.16 rather than this family's usual simulation-only real.
That is the whole reason the measure is det rather than the textbook smallest
eigenvalue: the accumulation is a rank-1 update, the determinant is a sum of
products and the trace is a sum, so no division, no square root and no
iteration reaches the emitted datapath. The order n and the method are both
fixed at export time, so each core carries one accumulation path and a
determinant unrolled into n! terms with their signs baked in – a flat sum of
products in the seven software targets, and a chained product in the three HDL
ones, where each multiply has to be brought back down by the fraction width.
The order is capped at 6, and the limit is n! rather than n³: a divide-free determinant means cofactor expansion, because every O(n³) route (LU, LDL′, Cholesky) needs a division and Cholesky a square root as well. The expansion costs n! products – 6 at n=3, 720 at n=6, 40,320 at n=8 – so an order above 6 is refused with that reason rather than emitted as a megabyte of unrolled arithmetic. trace is O(n) and has no such limit.
A normalized richness scalar is deliberately not an output.
det / (trace/n)n is dimensionless and equals 1 exactly when all
eigenvalues are equal, but it needs a runtime division and an n-th power, which
would carry all three HDL targets into simulation-only real for a
quantity that is already buildable downstream: n is known at design time, so
Gain, Product and Divide express it from the two ports this
block emits, and only the diagrams that ask for it pay for it.
Simulink bridge
None. The System Identification Toolbox has no block with this port
shape, and it is not installed on the machine this library is verified against,
so a bridge could not be parity-verified even if one were written. Every block in
this family registers Support::None for the same reason. It
therefore has no parity testbench, which is the documented consequence;
code export verification still covers it across all ten languages.
Notes
- Not a state space: the reduction to det is nonlinear in the state, so no A/B/C/D describes the block and model reduction correctly refuses it.
- Feed it the SAME regressor the estimator sees. The measure is only meaningful about the model being fitted – a richness verdict computed from a different vector answers a different question.
- A rank-deficient regressor gives det = 0 exactly, in every backend. If phi is built by scaling one signal into a column, S is rank 1 and det is identically zero for any n ≥ 2: that is the correct answer, and it is also the commonest way to wire the block up meaninglessly.
Code facts#
| Fact | Value |
|---|---|
| registered type | System_Identification/Validation/Excitation_Richness_Monitor |
| family | System_Identification/Validation |
| solver environment class | ICoreBlock_0_System_Identification_1_Validation_2_Excitation_Richness_Monitor |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/System_Identification/Validation/Excitation_Richness_Monitor/ICoreBlock_0_System_Identification_1_Validation_2_Excitation_Richness_Monitor.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/System_Identification/Validation/Excitation_Richness_Monitor/ICoreBlock_0_System_Identification_1_Validation_2_Excitation_Richness_Monitor.h |
| default size on canvas | 150 × 88 px |
| ports at insert | 1 in, 2 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | phi |
| 2 | out | ICoreDouble | det |
| 3 | out | ICoreDouble | trace |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Accumulation Method | Forgetting Factor%~%Sliding Window~~Forgetting Factor | — |
Forgetting Factor | 0.997 | — |
Window Length | 32 | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): no Simulink equivalent: the System Identification Toolbox has no block with this port shape, and the toolbox is not installed on the machine this library is verified against, so a bridge could not be parity-verified even if written
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Excitation Richness Monitor — the persistency-of-excitation guard S[k] = lambda * S[k-1] + phi phi' (Forgetting Factor) S[k] = SUM over the last N regressors (Sliding Window) outputs: det(S), trace(S)
Read the header before this file: it records why the measure is det AND trace rather than the textbook smallest eigenvalue, why the order is capped at 6 (the limit is n!, not n^3), why the three HDL targets are GENUINELY synthesizable here, and why a normalized scalar is deliberately left to downstream wiring.
Ten generators, one accumulation. Each emits the same four phases in the same order as advance() below:
- read phi from the port
- AGE the accumulator -- scale by lambda, or evict the regressor leaving the window
- add the rank-1 update phi phi' into S
- reduce S to det and trace, and write the two ports
Every bound is a compile-time constant and every operation is a multiply, an add or a subtract -- no division, no square root, no iteration -- which is what keeps the three HDL targets in real Q16.16 rather than in simulation-only
real.
Sample results#
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 639.9 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 0 … 28.12 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | 4 … 130.6 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category dynamic · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/System_Identification__Validation__Excitation_Richness_Monitor.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).