IIR Identification — System Identification/Offline
System_Identification/Offline/IIR_Identification · 2 input / 2 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
IIR Identification (offline)
System Identification / Offline
Fits a discrete transfer function to a measured input/output pair. It buffers both signals for the whole run, then solves once, after the last step, with a batch Levenberg-Marquardt fit, and writes the identified model to the run log.
Ports
- u – the excitation signal, scalar.
- y – the measured response, scalar.
- Num / Den – the fitted coefficient vectors, sized from the configured orders.
The output ports hold zeros for the whole run. The fit only completes after the last step, so there is no step at which a meaningful value could appear on them – the run log is where the result is. Use the Recursive IIR Identification block when the coefficients have to be live on a wire.
Parameters
- Numerator Order – the order of the fitted numerator.
- Denominator Order – the order of the fitted denominator, and so the model's order.
- Sampling Time (s) – the rate the samples are taken at, and the rate the identified model belongs to. Zero or less inherits the solver's rate.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text – but what every one of them emits is the block's actual per-step behaviour: zeros of the configured coefficient sizes on both output ports. That is not a stub; it is exactly what the block produces during a run.
The fit itself is deliberately not ported. A deployable core is a per-step scan with no end-of-run hook to run a batch solve in, and no target below double precision – the three fixed-point HDLs in particular – could carry a Levenberg-Marquardt solve meaningfully. Export the sibling Recursive IIR Identification block instead when the identified coefficients have to exist in the generated code: its update is per-step by construction.
Simulink bridge
Neither direction. System identification blocks have no Simulink equivalent, so the bridge reports this block with that reason instead of silently dropping it.
Notes
- Discrete only. Identification quality depends on the excitation: a signal that does not stir the dynamics cannot identify them.
Code facts#
| Fact | Value |
|---|---|
| registered type | System_Identification/Offline/IIR_Identification |
| family | System_Identification/Offline |
| solver environment class | ICoreBlock_0_System_Identification_1_Offline_2_IIR_Identification |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/System_Identification/Offline/IIR_Identification/ICoreBlock_0_System_Identification_1_Offline_2_IIR_Identification.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/System_Identification/Offline/IIR_Identification/ICoreBlock_0_System_Identification_1_Offline_2_IIR_Identification.h |
| default size on canvas | 90 × 70 px |
| ports at insert | 2 in, 2 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | in | ICoreDouble | — |
| 3 | out | ICoreDouble | — |
| 4 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Numerator Order | 1 | — |
Denominator Order | 2 | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): system identification blocks have no Simulink equivalent
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0Ports lists 3 entries for 4 ports (2 in, 2 out) — grouped, or one undocumented? a reader must say
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
Sample results#
| t | in ICoreDouble-Out-0 | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 [2x1] entry 0 | out ICoreDouble-Out-1 [3x1] entry 0 |
|---|---|---|---|---|
| 0 | -2 | -2 | [0, 0] | [0, 0, 0] |
| 0.4 | 0.5 | 0.5 | [0, 0] | [0, 0, 0] |
| 0.8 | -2 | -2 | [0, 0] | [0, 0, 0] |
| 1.2 | 0.5 | 0.5 | [0, 0] | [0, 0, 0] |
| 1.6 | -2 | -2 | [0, 0] | [0, 0, 0] |
| 2 | 0.5 | 0.5 | [0, 0] | [0, 0, 0] |
| 2.4 | -2 | -2 | [0, 0] | [0, 0, 0] |
| 2.8 | 0.5 | 0.5 | [0, 0] | [0, 0, 0] |
| 3.2 | -2 | -2 | [0, 0] | [0, 0, 0] |
| 3.6 | 0.5 | 0.5 | [0, 0] | [0, 0, 0] |
| 4 | -2 | -2 | [0, 0] | [0, 0, 0] |
| 4.4 | 0.5 | 0.5 | [0, 0] | [0, 0, 0] |
| 4.8 | -2 | -2 | [0, 0] | [0, 0, 0] |
| 5.2 | 0.5 | 0.5 | [0, 0] | [0, 0, 0] |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 0 |
ramp | Ramp: slope 1 from t = 0 | 0 … 0 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 0 … 0 |
step | Step: 0 -> 1 at t = 1 s | 0 … 0 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/System_Identification__Offline__IIR_Identification.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).