Nonlinear Grey Box Model — System Identification/Models
System_Identification/Models/Nonlinear_Grey_Box_Model · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Nonlinear Grey-Box Model
System Identification / Models
Simulates a nonlinear model whose equations you know and whose parameters you have identified: typed state and output equations over the states, the inputs, the named parameters and the time t,
y[k] = h(t, x, u, p), and either x[k+1] = f(t, x, u, p) (discrete) or dx/dt = f(t, x, u, p) (continuous),
with t = k·Ts. A continuous model is integrated with one Euler or
classical Runge-Kutta 4 step per sample at the block's sampling time, the
input held over the step. It is System Identification Toolbox's Simulink
Nonlinear Grey-Box Model block (an idnlgrey) run under the
FixedStepDiscrete, ode1 or ode4 solver, with the ODE file written as expressions
here.
The factory setting is a damped spring, dx/dt = [x2; −k·x1 − b·x2 + u], with k = 2 and b = 0.4, whose position is the output.
Ports
- u – the input, a column [m,1] in the order of Input Variables; a scalar that is ignored when there are none.
- y – the output, a column [ny,1] (ny = the entries of Output Equation).
Parameters
- State Variables – the n state names, 1 to 6.
- Input Variables – the m input names, 0 to 4.
- Parameter Names – the model's parameter names. States, inputs and parameters together may be at most 11 names; t is the time and is reserved.
- Parameter Values – one value per parameter name, in order.
- State Equation – f, a column of n expressions: the next state, or the state derivative.
- Output Equation – h, a column of 1 to 6 expressions.
- Initial State – x[0], n entries.
- Model Type – Discrete, Continuous (Euler) or Continuous (Runge-Kutta 4).
- Sampling Time (s) – the model's sample time, and a continuous model's integration step; it must be positive.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Each prints the same description of the sample that the simulation itself runs – the equations in the target's own syntax, the parameters baked in as constants – so every target does the same arithmetic in the same order.
⚠ The three HDL targets run in simulation-only real arithmetic, quantizing only at the port boundaries.
Simulink bridge
None (Support::None). Simulink's block takes an
idnlgrey object whose equations live in a MATLAB or C file, which a
model cannot carry; the bridge reports this block rather than dropping it
silently. Code export verification still covers it across all ten languages.
Notes
- Discrete only, and stateful: the state and a sample counter persist.
- ⚠ This block reproduces the Simulink block, not MATLAB's
sim(idnlgrey): MATLAB's sim reports the output of the last ODE-file call inside each sample (the Euler step's start, the fourth Runge-Kutta stage) and picks each step's input by a floating-point time comparison, so the two differ by up to a sample. - Variable-step solvers, noise, and parameter estimation are not offered.
Code facts#
| Fact | Value |
|---|---|
| registered type | System_Identification/Models/Nonlinear_Grey_Box_Model |
| family | System_Identification/Models |
| solver environment class | ICoreBlock_0_System_Identification_1_Models_2_Nonlinear_Grey_Box_Model |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/System_Identification/Models/Nonlinear_Grey_Box_Model/ICoreBlock_0_System_Identification_1_Models_2_Nonlinear_Grey_Box_Model.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/System_Identification/Models/Nonlinear_Grey_Box_Model/ICoreBlock_0_System_Identification_1_Models_2_Nonlinear_Grey_Box_Model.h |
| default size on canvas | 160 × 80 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | out | ICoreDouble | y |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
State Variables | x1 x2 | — |
Input Variables | u | — |
Parameter Names | k b | — |
Parameter Values | [2 0.4] | — |
State Equation | [x2; -k*x1 - b*x2 + u] | — |
Output Equation | x1 | — |
Initial State | [1; 0] | — |
Model Type | Discrete%~%Continuous (Euler)%~%Continuous (Runge-Kutta 4… | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): Simulink's Nonlinear Grey-Box Model block takes an idnlgrey object whose equations live in a MATLAB or C file, which a model cannot carry. The block is reported rather than dropped when a model crosses
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Nonlinear Grey-Box Model -- System Identification Toolbox's idnlgrey block, typed equations y[k] = h(t_k, x_k, u_k, p); x_{k+1} = f(...) (discrete), or one Euler / RK4 step of dx/dt = f at the block's rate (continuous); t_k = k*Ts
The arithmetic is ICoreGreyBoxSupport's. ⚠ MEASURED AGAINST R2026a's Simulink block (slident/Models/Nonlinear Grey-Box Model, the MATLAB S-function sfidnlgrey) on 40 random models under FixedStepDiscrete, ode1 and ode4: 25 of 39 finite runs bit for bit, the rest within 5.2e-16. MATLAB's
sim(idnlgrey)differs from its own block -- see the support header.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.