Nonlinear ARX Model — System Identification/Models
System_Identification/Models/Nonlinear_ARX_Model · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Nonlinear ARX Model
System Identification / Models
Simulates a single-input single-output nonlinear ARX model: the output is a nonlinear function of past outputs and of current and past inputs,
y(t) = F( y(t−1), …, y(t−na), u(t), u(t−1), …, u(t−L) ).
F is typed as an expression over the regressors, named by their lag:
y1 … y<na> are the past outputs and
u0 … u<L> the current and past inputs, so
0.5*y1 - 0.2*y2 + 0.4*u0 + 0.3*sin(u1) + 0.2*y1*u1 is a model with two
output lags and one input lag. It is System Identification Toolbox's idnlarx
model and the Simulink Nonlinear ARX Model block, for a map written out as a
formula.
Ports
- u – the input, a scalar.
- y – the output, a scalar.
Parameters
- Output Lags – na, how many past outputs the map may name: 0 to 8.
- Input Lags – L, how many past inputs beyond the current one: 0 to 8. na + L + 1 is at most 12.
- Map – F, one expression over
y1..y<na>andu0..u<L>, with the usual operators and elementary functions (sin, cos, exp, log, sqrt, tanh, abs, powers). A regressor it does not name is simply unused. - Initial Past Output – the value every past output holds before the first sample.
- Initial Past Input – the value every past input holds before the first sample.
- Sampling Time (s) – the model's sample time; zero or less inherits the solver's rate.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Each prints the same description of the step that the simulation itself runs, so every target does the same arithmetic in the same order; the map is printed as that target's own expression.
⚠ The three HDL targets run in simulation-only real arithmetic, quantizing only at the port boundaries.
Simulink bridge
None (Support::None). Simulink's block takes an
idnlarx object from the workspace, which a model file does not carry;
the bridge reports this block rather than dropping it silently. Code export
verification still covers it across all ten languages.
Notes
- Discrete only, and stateful: the past outputs and inputs persist.
- ⚠ To copy a model from MATLAB, estimate it with
nlarxOptions('Normalize', false): with the default normalization idnlarx centers and scales every regressor before the map sees it, so the same coefficients describe a different model. - Only single-input single-output models with the map given as a formula: sigmoid and wavelet networks, trees, and custom regressor sets over other signals are not offered.
Code facts#
| Fact | Value |
|---|---|
| registered type | System_Identification/Models/Nonlinear_ARX_Model |
| family | System_Identification/Models |
| solver environment class | ICoreBlock_0_System_Identification_1_Models_2_Nonlinear_ARX_Model |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/System_Identification/Models/Nonlinear_ARX_Model/ICoreBlock_0_System_Identification_1_Models_2_Nonlinear_ARX_Model.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/System_Identification/Models/Nonlinear_ARX_Model/ICoreBlock_0_System_Identification_1_Models_2_Nonlinear_ARX_Model.h |
| default size on canvas | 160 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | out | ICoreDouble | y |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Output Lags | 2 | — |
Input Lags | 1 | — |
Map | 0.5*y1 - 0.2*y2 + 0.4*u0 + 0.3*sin(u1) + 0.2*y1*u1 | — |
Initial Past Output | 0 | — |
Initial Past Input | 0 | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): Simulink's Nonlinear ARX Model block takes an idnlarx object from the workspace, which a model file does not carry. The block is reported rather than dropped when a model crosses
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Nonlinear ARX Model -- System Identification Toolbox's idnlarx, single input and output y(t) = F( y(t-1), ..., y(t-na), u(t), u(t-1), ..., u(t-L) )
F is typed over the regressors y1..y<na>, u0..u<L> and compiled by the symbolic engine; the arithmetic is ICoreNonlinearArxSupport's.
⚠ MEASURED AGAINST R2026a's idnlarx
simon 24 random models (na 0..3, L 0..3, linear, product, power and sin regressors, Normalize = false): at worst 3.9e-16 relative over 150 samples each; and the emitted Python is bit-identical to the live run, from a configured initial history, on all 24.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.