Model Type Converter — System Identification/Estimators
System_Identification/Estimators/Model_Type_Converter · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Model Type Converter
System Identification / Estimators
Turns a polynomial model on a bus into the same model in state-space form on a bus, every step: the transfer function B/A (ARX, ARMAX) or B/F (OE, BJ) that an online estimator identified, as the matrices A, B, C and D of x(k+1) = A x(k) + B u(k), y(k) = C x(k) + D u(k). The form is MATLAB's observer canonical form, as Simulink's block gives it: with the polynomials normalized by the leading denominator coefficient, A's first column is minus the denominator's remaining coefficients and its superdiagonal is ones, C picks the first state, D is the numerator's leading coefficient, and B(i) = b(i+1) − a(i+1)·D.
Ports
- u – a bus holding the polynomial model, as Simulink's Recursive Polynomial Model Estimator gives it: elements A and B for ARX and ARMAX, B and F for OE and BJ, each a row or column of coefficients in powers of z−1, leading coefficient first. Other elements (C, D, Ts) may be on the bus and are not read.
- y – a bus of four elements: A [n,n], B [n,1], C [1,n] and D [1,1], where n is the longer polynomial's length minus one. A static gain (both polynomials one coefficient long) gives one state: A = 0, B = 0, C = 1 and D the gain.
Parameters
- Input Model Type – ARX (the default), ARMAX, OE or BJ: which elements hold the numerator and the denominator (B and A, or B and F).
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
When a run is refused
An input that is not a bus, a bus without the two elements the model type reads, or an element that is not a row or a column of numbers.
Code export
Six targets: Python, MATLAB, Java, Rust, C and C++, each reading the input bus's two elements and writing the four of the output bus, with the arithmetic in the live block's order. The hardware targets (VHDL, Verilog, SystemVerilog) and PLC Structured Text carry no bus, so an export to one stops and names the block.
Simulink bridge
Import and export, mapped to slident/Estimators/Model Type
Converter: Input Model Type ↔ InputModelType,
1:1. The Simulink block has no SampleTime, so the rate stays on the ICore
side. Its B output is one-dimensional, [n]; here it is a column,
[n,1].
Notes
- Algebraic and stateless: the outputs depend only on this sample's input.
- A zero leading denominator coefficient is taken as eps (2.2×10−16), as Simulink's block does, so the matrices become enormous rather than the run stopping.
- Verified against R2026a: the arithmetic answers what Simulink's block answers, bit for bit, on 30 random non-monic polynomials of lengths 1 to 5, and on ARX, ARMAX, OE and BJ buses.
Code facts#
| Fact | Value |
|---|---|
| registered type | System_Identification/Estimators/Model_Type_Converter |
| family | System_Identification/Estimators |
| solver environment class | ICoreBlock_0_System_Identification_1_Estimators_2_Model_Type_Converter |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/System_Identification/Estimators/Model_Type_Converter/ICoreBlock_0_System_Identification_1_Estimators_2_Model_Type_Converter.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/System_Identification/Estimators/Model_Type_Converter/ICoreBlock_0_System_Identification_1_Estimators_2_Model_Type_Converter.h |
| default size on canvas | 120 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++ |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreBus | u |
| 2 | out | ICoreBus | y |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Input Model Type | ARX%~%ARMAX%~%OE%~%BJ~~ARX | InputModelType |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | slident/Estimators/Model Type Converter |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Input Model Type | InputModelType | ARX → ARX, ARMAX → ARMAX, OE → OE, BJ → BJ |
Caveat (shown to the user): One bus in and one bus out; the output's B is 1-D [n] in Simulink and a column [n,1] here. The Simulink block has no SampleTime, so the rate stays on the ICore side
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Model Type Converter -- a polynomial model on a bus as a state-space model on a bus slident/Estimators/Model Type Converter, MEASURED on R2026a 2026-10-02 (BLOCKS_TO_ADD_ TOOLBOXES.md slident, on FEATURES_TO_ADD.md BF1): MaskType idModelTypeConverter, one bus in (u) and one bus out (y), one parameter, InputModelType ARX (default) | ARMAX | OE | BJ. Inside, a Bus Selector picks (B, A) for ARX and ARMAX or (B, F) for OE and BJ -- C, D and Ts are not read -- and an S-Function turns num/den into A, B, C, D, which a Bus Creator packs.
The arithmetic, fitted BIT FOR BIT on 30 random polynomials (lengths 1..5, non-monic) and checked on the measured shapes: both polynomials padded with trailing zeros to one length L = n + 1; a0 = den(1), and a0 == 0 is taken as eps (2.2e-16), as R2026a does (measured: den [0 1 0.5] answers 1/eps); an = den / a0, bn = num / a0; D = bn(1); A(i, 1) = -an(i + 1), A(i, i + 1) = 1 (observer canonical form), C = [1 0 ... 0], B(i) = bn(i + 1) - an(i + 1) * D; L = 1 (a static gain): A = 0, B = 0, C = 1, D = bn(1) -- one state, as R2026a gives it. Sizes: A [n n], B [n] (1-D in Simulink; a column [n,1] here), C [1 n], D [1 1].
ALGEBRAIC and STATELESS.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.