Iddata Sink — System Identification/Data
System_Identification/Data/Iddata_Sink · 2 input / 0 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Iddata Sink
System Identification / Data
Records a system's input u and output y at its own sample time
and, when the run ends, leaves them in the project's variables space as one
iddata, the time-domain data object MATLAB's System Identification
Toolbox estimates models from: OutputData (one row per sample, one
column per output channel), InputData (the same for the inputs),
Ts and Tstart. A second run replaces it.
Ports
- u – the input data, any size: each element is one channel (one
column of
InputData). - y – the output data, the same way (
OutputData). - No outputs.
Parameters
- Dataset Name – the variable the iddata is left in, a name
MATLAB accepts (a letter, then letters, digits and underscores). Default
data, as in MATLAB. - Sampling Time (s) – the iddata's sample time
Ts, which is also the rate the block samples at, whatever the model's step: at 0.3 s in a model stepping 0.1 s to t = 1 it records the four samples at 0, 0.3, 0.6 and 0.9. It must be a positive number: an inherited rate is refused, as MATLAB refuses it. Default 0.1, as in MATLAB.
What the variable holds
A record of the four numeric properties, which a console line reads as
data.OutputData, data.InputData, data.Ts
and data.Tstart, and which the System Identification commands take
as u, y and Ts. MATLAB's iddata also
holds the character properties Domain ('Time'),
InterSample ('foh'), TimeUnit
('seconds') and the channel names u1… and
y1…; a record here holds numbers only, so reading one of those
says so by name.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text, as a named body that does nothing: an exported core has no variables space to leave an object in.
Simulink bridge
Import and export, mapped to slident/Iddata Sink: Dataset Name
↔ datasetname and Sampling Time (s) ↔
Ts. Under Simulink's default ReturnWorkspaceOutputs = on
the iddata is a field of the simulation output, not a workspace variable.
Notes
- The block records at the instants the model steps through: a sample time that is a multiple of the model's step records every one of its samples. One that is not records only the instants the two share, where Simulink would add its own sample hits to the run.
- When the run is refused or stopped before its first sample, nothing is left.
Code facts#
| Fact | Value |
|---|---|
| registered type | System_Identification/Data/Iddata_Sink |
| family | System_Identification/Data |
| solver environment class | ICoreBlock_0_System_Identification_1_Data_2_Iddata_Sink |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/System_Identification/Data/Iddata_Sink/ICoreBlock_0_System_Identification_1_Data_2_Iddata_Sink.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/System_Identification/Data/Iddata_Sink/ICoreBlock_0_System_Identification_1_Data_2_Iddata_Sink.h |
| default size on canvas | 80 × 80 px |
| ports at insert | 2 in, 0 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | in | ICoreDouble | y |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Dataset Name | data | datasetname |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | slident/Iddata Sink |
| port-count rule | PortsParam:: |
SampleTime parameter | yes |
| rate parameter name | Ts |
| deliberately not crossed | isu, isy |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Dataset Name | datasetname | passes through |
Caveat (shown to the user): the block's rate IS the iddata's Ts, so it crosses as the mask's own
Tsrather
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Iddata Sink -- u and y at the block's own sample time, left as an iddata when the run ends Measured on R2026a (FEATURES_TO_ADD.md §F.BF18, BF18.1):
slident/Iddata Sinkis a masked subsystem over the S-functionidentsink, 2 inputs (1 = u, 2 = y), no outputs, the mask parametersdatasetname(defaultdata) andTs(default 0.1), and two hidden switches that change nothing measured with both ports wired. It writes ONE time-domain iddata at the end of the run: under a 0.1 s fixed step to t = 1, OutputData and InputData are 11 x 1 (t = 0 ... 1), Ts = 0.1, Tstart = 0; a 2-element u gives InputData N x 2. It samples at its OWN Ts, not the model's: Ts = 0.3 in a 0.1 model to t = 1 logs 4 samples, y = [0 0.3 0.6 0.9].Ts = -1is refused: "Invalid sample time. Choose a positive scalar."The record (numbers only, the character properties withheld by name) and the end-of-run declare are ICoreWorkspaceObjects' (BF18.2), the same path a To Workspace's time series takes.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.