Switch Case — Private/Subsystem Components
Private/Subsystem_Components/Switch_Case · 1 input / 2 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Switch Case
Control Systems / Ports And Subsystems
Chooses, each step, which one of the action subsystems it drives runs: the case whose values hold the input truncated toward zero, else the default output, else none. Simulink’s Switch Case block (BlockType=SwitchCase). Each subsystem it drives holds an Action Port; the library’s Subsystem Templates hold a ready-made Switch Case Action Subsystem.
Ports
- Inputs – one, a scalar.
- Outputs – one per case, and one more for default while Show default case is On. Each drives the Action input of one action subsystem.
Parameters
- Case conditions – a cell of 32-bit integers or integer vectors, one output each:
{1,[2 3]}.{1}(default). No value may appear twice. - Show default case – On (default) gives the default output.
Notes
- Each output drives exactly one action subsystem, through its Action input. The port counts are checked against the parameters before a run, by name.
- It runs: each step the input is truncated toward zero, as Simulink does (−2.5 is −2, not −3), and the first case listing that value runs its subsystem; the default runs when none does and Show default case is On. NaN runs the default. The input is one number; a vector is refused.
Code export
All ten targets. The generated code compares the input, truncated toward zero, with each case's values and writes 1 on the output it chooses and 0 on the rest; NaN and anything past the cases reach the default. VHDL, Verilog, SystemVerilog and PLC-ST test the range of inputs a case value covers, which is exact in their fixed-point and LREAL carriers.
Simulink bridge
Both directions, as simulink/Ports & Subsystems/Switch Case.
Case conditions goes to CaseConditions and Show default
case to ShowDefaultCase (On and Off to on and off). No parameter
carries a port count: Simulink derives the outputs from these two, and an import
does the same. "Sampling Time (s)" goes to SampleTime, as
on every block.
Code facts#
| Fact | Value |
|---|---|
| registered type | Private/Subsystem_Components/Switch_Case |
| family | Private/Subsystem_Components |
| solver environment class | ICoreBlock_0_Private_1_Subsystem_Components_2_Switch_Case |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Switch_Case/ICoreBlock_0_Private_1_Subsystem_Components_2_Switch_Case.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Switch_Case/ICoreBlock_0_Private_1_Subsystem_Components_2_Switch_Case.h |
| default size on canvas | 90 × 80 px |
| ports at insert | 1 in, 2 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u1 |
| 2 | out | ICoreDouble | case 1 |
| 3 | out | ICoreDouble | default |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Case conditions | {1} | CaseConditions |
Show default case | Off%~%On~~On | ShowDefaultCase |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Ports & Subsystems/Switch Case |
| port-count rule | PortsParam::ActionDriverPorts |
SampleTime parameter | yes |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Case conditions | CaseConditions | passes through |
Show default case | ShowDefaultCase | On → on, Off → off |
Caveat (shown to the user): Simulink's Switch Case block; its outputs follow its parameters on both sides (FEATURES_TO_ADD.md BF8.5).
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
tools/docs/check_block_descriptions.py(P7.1) could not be run when this page was generated, so no verdict is shown. Run it yourself; a page cannot claim an agreement it did not measure.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.