Subsystem Output Gate — Private/Subsystem Components

Subsystem Output Gate

Subsystem Components

Sends a signal out of a subsystem. Placing one inside a subsystem adds an output port to the subsystem block on the level above; whatever is wired in here leaves through that port.

Ports

• Inputs – one by default, and the count is user-editable. Each one is paired with a port on the subsystem block outside, and hands its signal size to that side.

Parameters

• Output when disabled – read only in an enabled, triggered or resettable subsystem, on the steps it does not run: held (default) keeps the last value; reset writes the Initial output.
• Initial output – what the port reads before the subsystem first runs, and while it is disabled under reset. [] (default) is zero; a scalar fills every element.
• Unit – the physical unit of the signal leaving here, as Simulink's Outport has it: inherit (default) passes on the unit the signal arrives with; any other text (m, rad/s) assigns that unit to the subsystem's output port outside and to every wire it reaches. A signal arriving in a different unit of the same quantity is converted here, as Simulink's automatic unit conversion does at an Outport too (m arriving where cm is set leaves as 300 for 3), and the run says so; a unit of another quantity, or one not in ICore's unit table, passes unconverted with a warning. The model settings unitsInconsistencyMessage and automaticUnitConversions turn the warnings and the conversion off. The text is not checked against a unit list – Simulink keeps an undefined unit as written too. Code export carries the conversion in all ten targets.

Notes

• The pairing is what makes the gate work: an unpaired gate has nothing outside to write to, and the run stops with the block's path.
• The gate itself computes nothing – it forwards. Sizes propagate outward through it, so the subsystem block's output ports size themselves from the diagram inside.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. On the top-level subsystem the gates are what become the generated core's outputs; deeper down they are plain signal forwarding. Order matters: a core's outputs are matched by gate creation order, not by name – the same rule the parity rigs follow.

Simulink bridge

Handled structurally, not through the block catalog. The bridge rebuilds subsystem boundaries on the far side rather than mapping this block to a library primitive, which is why it carries no parameter mapping.