Subsystem Input Gate — Private/Subsystem Components
Private/Subsystem_Components/Subsystem_Input_Gate · 0 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Subsystem Input Gate
Subsystem Components
Brings a signal into a subsystem. Placing one inside a subsystem adds an input port to the subsystem block on the level above; whatever is wired to that port arrives here.
Ports
- Outputs – one by default, and the count is user-editable. Each one is paired with a port on the subsystem block outside, and takes its signal size from that side.
Notes
- The pairing is what makes the gate work: an unpaired gate has nothing outside to read from, and the run stops with the block's path.
- The gate itself computes nothing – it forwards. Sizes propagate inward through it, so the diagram inside sizes itself from what is connected outside.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. On the top-level subsystem the gates are what become the generated core's inputs; deeper down they are plain signal forwarding. Order matters: a core's inputs are matched by gate creation order, not by name – the same rule the parity rigs follow.
Simulink bridge
Handled structurally, not through the block catalog. The bridge rebuilds subsystem boundaries on the far side rather than mapping this block to a library primitive, which is why it carries no parameter mapping.
Code facts#
| Fact | Value |
|---|---|
| registered type | Private/Subsystem_Components/Subsystem_Input_Gate |
| family | Private/Subsystem_Components |
| solver environment class | ICoreBlock_0_Private_1_Subsystem_Components_2_Subsystem_Input_Gate |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Subsystem_Input_Gate/ICoreBlock_0_Private_1_Subsystem_Components_2_Subsystem_Input_Gate.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Subsystem_Input_Gate/ICoreBlock_0_Private_1_Subsystem_Components_2_Subsystem_Input_Gate.h |
| default size on canvas | 120 × 40 px |
| ports at insert | 0 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): handled structurally by the bridge, not via the catalog
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
tools/docs/check_block_descriptions.py(P7.1) could not be run when this page was generated, so no verdict is shown. Run it yourself; a page cannot claim an agreement it did not measure.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.