Subsystem Input Gate — Private/Subsystem Components

Subsystem Input Gate

Subsystem Components

Brings a signal into a subsystem. Placing one inside a subsystem adds an input port to the subsystem block on the level above; whatever is wired to that port arrives here.

Ports

• Outputs – one by default, and the count is user-editable. Each one is paired with a port on the subsystem block outside, and takes its signal size from that side.

Parameters

• Unit – the physical unit of the signal entering here, as Simulink's Inport has it: inherit (default) takes whatever unit arrives on the wire outside; any other text (m, rad/s) assigns that unit to the signal inside the subsystem and to every wire it reaches. A signal arriving in a different unit of the same quantity is converted here, as Simulink's automatic unit conversion does (m arriving where cm is set reads 300 for 3; degC into degF is affine), and the run says so; a unit of another quantity, or one not in ICore's unit table, passes unconverted with a warning. The model settings unitsInconsistencyMessage and automaticUnitConversions turn the warnings and the conversion off. A unit arrives only along wires and through other subsystem ports: an ordinary block between two ports passes none on. The text is not checked against a unit list – Simulink keeps an undefined unit as written too. Code export carries the conversion in all ten targets.

Notes

• The pairing is what makes the gate work: an unpaired gate has nothing outside to read from, and the run stops with the block's path.
• The gate itself computes nothing – it forwards. Sizes propagate inward through it, so the diagram inside sizes itself from what is connected outside.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. On the top-level subsystem the gates are what become the generated core's inputs; deeper down they are plain signal forwarding. Order matters: a core's inputs are matched by gate creation order, not by name – the same rule the parity rigs follow.

Simulink bridge

Handled structurally, not through the block catalog. The bridge rebuilds subsystem boundaries on the far side rather than mapping this block to a library primitive, which is why it carries no parameter mapping.