If — Private/Subsystem Components

If

Control Systems / Ports And Subsystems

Chooses, each step, which one of the action subsystems it drives runs: the first output whose condition holds, in order, else the else output, else none. Simulink’s If block (BlockType=If). Each subsystem it drives holds an Action Port; the library’s Subsystem Templates hold a ready-made If Action Subsystem.

Ports

• Inputs – Number of inputs of them, u1 … un, the names the conditions use.
• Outputs – one for the If expression, one per Elseif expressions entry, and one more for else while Show else condition is On. Each drives the Action input of one action subsystem.

Parameters

• Number of inputs – 1 (default).
• If expression – a MATLAB-style scalar condition over u1 … un: ~, ~=, &&, ||, u1(k), arithmetic. u1 > 0 (default).
• Elseif expressions – comma-separated, one output each; none by default. Every comma separates two expressions, as in Simulink, so a condition with a comma inside it (max(u1, u2) > 0, u1(2,1) > 0) belongs in the If expression; in this list it is refused by name.
• Show else condition – On (default) gives the else output.

Notes

• Each output drives exactly one action subsystem, through its Action input. The port counts are checked against the parameters before a run, by name.
• It runs: each step the expressions are evaluated in order and the first true one's subsystem runs, or the else subsystem, or none. A nonzero value is true. The grammar is MATLAB's reduced to a scalar: arithmetic and ^, comparisons, ~, &, |, &&, ||, u1(k) and u1(r,c) with end (column-major), true, false, abs, min, max and a few more functions, and a name from the variables space. C syntax (!, !=, u1[2]), an input past n, an index out of range and a condition that is not one number are refused by name, with Simulink’s message ID – an If never vectorises.

Code export

All ten targets. Each step the generated code writes 1 on the output it chooses and 0 on the rest, and the action subsystem behind it runs under its guard. Python, MATLAB, Java, Rust, C++ and C carry the whole grammar, with the same rules as the simulation. VHDL, Verilog and SystemVerilog carry comparisons, ~, &, |, && and || over + and - of numbers and input elements; PLC-ST adds *, /, ^, abs, sqrt, exp, log, sin, cos, tan, min and max. An expression a target does not carry, and an index that depends on an input's value, are refused by name.

Simulink bridge

Both directions, as simulink/Ports & Subsystems/If. Number of inputs goes to NumInputs, If expression to IfExpression, Elseif expressions to ElseIfExpressions and Show else condition to ShowElse (On and Off to on and off). No parameter carries a port count: Simulink derives both lists from these four, and an import does the same. Simulink’s If knows abs, sqrt, exp, log, sin, cos, tan, floor, ceil, sign, mod and rem but not round, fix, min or max: a condition using one of those four still exports, and the export says, in its report and in the script, that Simulink will not compile it. "Sampling Time (s)" goes to SampleTime, as on every block.