Function Call Split — Private/Subsystem Components
Private/Subsystem_Components/Function_Call_Split · 1 input / 2 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Function-Call Split
Control Systems / Ports And Subsystems
Lets one function call run several function-call subsystems, in a fixed
order: each call that reaches it runs the subsystem output 1 reaches, then the
one output 2 reaches, and so on, before the next call. A call line cannot simply
be branched; this block is how one call reaches more than one subsystem.
Simulink’s Function-Call Split
(BlockType=FunctionCallSplit).
Ports
- Input – one function call (badge
fcn), from a Function-Call Generator, another Split, or a called subsystem’s output. A wide call (one from a Number of iterations with several elements) is refused before a run, as Simulink refuses it; split it with a Demux first. - Outputs – two by default, and the count is user-editable; at least two. Each is a function call, wired to a subsystem whose Trigger port has Trigger type function-call, or to another Split.
Parameters
None besides the output count. The order is the output order: output 1 runs first, whatever the subsystems are called and wherever they sit. A Split on an output runs everything it reaches before the next output of this one.
Code export
Python, MATLAB, Java, Rust, C, C++ and PLC Structured Text: each output carries the caller’s count, and each subsystem runs as a loop of that many passes at its place in the step, placed in output order. A caller that calls more than once per step is refused, because Simulink runs the outputs alternately (1, 2, 1, 2) and the exported loops would run each subsystem’s calls together; so is an order that the diagram’s own wiring forces against the output order. VHDL, Verilog and SystemVerilog refuse a function call by name.
Simulink bridge
Import and export, as built-in/FunctionCallSplit: the output count
↔ NumOutputPorts. OutputPortLayout and
IconShape only draw the icon and are not carried.
Notes
- It keeps no state and calls nothing of its own: it runs only when its caller calls.
- One output is refused: Simulink accepts two or more.
Code facts#
| Fact | Value |
|---|---|
| registered type | Private/Subsystem_Components/Function_Call_Split |
| family | Private/Subsystem_Components |
| solver environment class | ICoreBlock_0_Private_1_Subsystem_Components_2_Function_Call_Split |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Function_Call_Split/ICoreBlock_0_Private_1_Subsystem_Components_2_Function_Call_Split.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Function_Call_Split/ICoreBlock_0_Private_1_Subsystem_Components_2_Function_Call_Split.h |
| default size on canvas | 60 × 70 px |
| ports at insert | 1 in, 2 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreFunctionCall | — |
| 2 | out | ICoreFunctionCall | — |
| 3 | out | ICoreFunctionCall | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | built-in/FunctionCallSplit |
| port-count rule | PortsParam::FcnCallSplitOutputs |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
Caveat (shown to the user): "Simulink's Function-Call Split: the output count crosses as NumOutputPorts
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
tools/docs/check_block_descriptions.py(P7.1) could not be run when this page was generated, so no verdict is shown. Run it yourself; a page cannot claim an agreement it did not measure.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Function-Call Split -- one function call in, two or more out, run in port order Simulink's Function-Call Split (BlockType=FunctionCallSplit). It is a CARRIER, not a caller: when its caller calls, ICoreSubsystemActivity::dispatchCalls walks through it and runs what output 1 reaches, then output 2, depth first, once per call -- two calls run S1, S2, S1, S2 (R2026a, measured: a data store written 10*DS + k gives 1212 a step). Its own solve only copies the count onto every output, which is what code export's called-subsystem loops read at their faces.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.