For Iterator — Private/Subsystem Components

For Iterator

Control Systems / Ports And Subsystems

Makes the subsystem it sits in a For Iterator subsystem: each step, the subsystem runs a counted number of times, and what is seen outside is the last pass. Simulink’s For Iterator block (BlockType=ForIterator). To make one, place this block in a subsystem, or insert the ready-made For Iterator Subsystem from the library’s Subsystem Templates.

Ports

• Inputs – none while Iteration source is internal; one, the count, while it is external. Add or remove it to match.
• Outputs – one, the iteration number, while Show iteration port is On (the default); none while it is Off.

Parameters

• Reset states – held (default) carries states from one step to the next; reset re-seeds them once per step, before the first pass, never between passes.
• Iteration source – internal (default) counts to the Iteration limit; external reads the count from the input port.
• Iteration limit – the count, when internal. 0 runs nothing.
• External increment – Off (default).
• Show iteration port – On (default) gives the iteration-number output.
• Index mode – One-based (default): the output reads 1..N; zero-based reads 0..N-1.
• Iteration variable data type – int32 (default). It bounds the count: int8 allows 0 to 126.

Notes

• A subsystem is iterated by one iterator block at most, and the block has to sit inside a subsystem, never at the top level. A port count or a count that disagrees with the parameters is refused before a run, by name.
• A simulation runs the subsystem’s blocks once per pass, all at the step’s time, and what is seen outside is the last pass. Inside, every block inherits its rate (-1) or is constant; a continuous block, a block with its own rate and a Discrete-Time Integrator (elapsed time) are refused by name, as R2026a refuses them.

Code export

The subsystem exports as a loop around its blocks, with the same passes as the simulation: Python, MATLAB, Java, Rust, C, C++ and PLC Structured Text carry every limit and an external count. VHDL, Verilog and SystemVerilog run at most one pass per clock tick, so they carry an internal Iteration limit of 0 or 1 and refuse any other by name. Reset states reset is carried wherever the loop is. A block that keeps its own clock is set back before every pass, since every pass runs at the step’s time.

Simulink bridge

Import and export, mapped to built-in/ForIterator; the library’s For Iterator Subsystem imports with what R2026a puts in it (an In1, the For Iterator, an Out1, In1 wired to Out1, atomic). Every parameter crosses: Reset states to ResetStates, Iteration source to IterationSource, Iteration limit to IterationLimit, External increment to ExternalIncrement, Show iteration port to ShowIterationPort, Index mode to IndexMode and Iteration variable data type to IterationVariableDataType. Its ports follow its parameters on both sides.