For Each — Private/Subsystem Components

For Each

Control Systems / Ports And Subsystems

Makes the subsystem it sits in a For Each subsystem: each step, the subsystem runs once per slice of its partitioned inputs, each slice with its own copy of every state, and the outputs are the slices concatenated. Simulink’s For Each block (BlockType=ForEach). To make one, place this block in a subsystem, or insert the ready-made For Each Subsystem from the library’s Subsystem Templates.

Ports

• None. What it partitions is the subsystem’s own inputs, one entry per input in each list below, or one entry for all of them.

Parameters

• Input partition – on or off per input, comma-separated. At least one input must be partitioned; an input that is off reaches every slice whole.
• Input partition dimension – the dimension each input is sliced along, 1 or 2. A 1×n row partitioned along dimension 1 is a vector and is sliced along its length.
• Input partition width – the width of one slice.
• Input partition offset – the step between slices beyond the width; negative overlaps them. A length L gives (L + offset) / (width + offset) slices, and must divide evenly.
• Output concatenation dimension – per output, the dimension the slices are joined on. When every partitioned input is a row vector, row slices joined along dimension 1 make a longer row.
• Show iteration index – Off (default). On is refused: the block has no output port yet.
• Iteration index data type – int32 (default).
• Specified number of iterations – -1 (default): as many as the partition gives. Any other value must equal that number.

Notes

• Every partitioned input must give the same number of slices, and a size that does not divide into slices is refused before a run, in Simulink’s words.
• Each slice keeps its own copy of every state inside, a continuous one included, and its own clock. A block whose state cannot be copied per slice is refused before a run, by name, rather than letting the slices share one.
• A subsystem is iterated by one iterator block at most, and the block has to sit inside a subsystem, never at the top level.

Code export

The subsystem exports as a loop over its slices, each slice with its own copy of every state inside, swapped in for its pass: Python, MATLAB, Java, Rust, C, C++ and PLC Structured Text. VHDL, Verilog and SystemVerilog would need one copy of the hardware per slice and refuse it by name. Also refused by name: a For Each inside a For Each, and a sliced input or joined output that is not a double.

Simulink bridge

Import and export, mapped to built-in/ForEach; the library’s For Each Subsystem imports with what R2026a puts in it (an In1, the For Each, an Out1, In1 wired to Out1, atomic). Input partition, Input partition dimension, Input partition width, Input partition offset and Output concatenation dimension cross as Simulink’s cells (InputPartition, InputPartitionDimension, InputPartitionWidth, InputPartitionOffset, OutputConcatenationDimension), one entry per Inport or Outport; Show iteration index to ShowIterationIndex, Iteration index data type to IterationIndexDataType and Specified number of iterations to SpecifiedNumIters. Mask-parameter partitioning does not cross: no ICore block has a mask.