Event Listener — Private/Subsystem Components
Private/Subsystem_Components/Event_Listener · 0 input / 0 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Event Listener
Control Systems / Ports And Subsystems
Makes the subsystem it sits in run on a model event instead of on the steps:
an Initialize Function, a Terminate Function, a Reset
Function or a Reinitialize Function. Simulink’s Event
Listener (BlockType=EventListener), the block inside each of those
four library subsystems. To make one, place this block in a
subsystem.
Ports
None. It adds no port to the subsystem’s face either.
Parameters
- Event type – Initialize (default): the subsystem runs once, before the first step’s outputs, so what it writes – a data store, a State Writer’s state – is what the first step reads. Terminate: it runs once, after the last step. Reset and Reinitialize: it never runs, as in a Simulink top model, where those events are never raised.
Notes
- The subsystem’s outputs read their Initial output until it runs, and hold what it wrote after.
- Refused before a run, as Simulink refuses them: a listener outside a subsystem, two in one subsystem, a listener beside an Enable, Trigger, Reset or Action port, a block with states inside the subsystem, a sampling time inside that is neither inherited nor constant, an input of the subsystem driven by any block, even through the inputs of the subsystems around it (only a model input may drive one), and two Initialize (or two Terminate) Functions counted in one non-virtual subsystem. A Terminate Function’s output may not be wired: through the run Simulink reads its Initial output, except that it folds a constant inside into it.
- When there are several, an inner Initialize Function runs before the one in the subsystem that holds it.
Code export
All ten targets carry an Initialize Function: its blocks run under a guard that fires on the first step only, at the head of the step, before every block that can read what it writes. A Reset or Reinitialize Function is carried as a run that never fires. A Terminate Function is refused by name in every target: it runs after the last step, and an exported core is stepped by its caller with no end of run. The block itself writes nothing.
Simulink bridge
Both directions, as built-in/EventListener: Event type
↔ EventType, one value for one value. It has no
SampleTime. The library’s Initialize Function,
Terminate Function, Reset Function and Reinitialize
Function import as a subsystem holding one, with what Simulink puts inside
them: a Constant of 0 into a State Writer, or a State Reader into a Terminator.
A script’s delete_block of one of those defaults is applied.
EventName, which names a Reset event, is not carried.
Code facts#
| Fact | Value |
|---|---|
| registered type | Private/Subsystem_Components/Event_Listener |
| family | Private/Subsystem_Components |
| solver environment class | ICoreBlock_0_Private_1_Subsystem_Components_2_Event_Listener |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Event_Listener/ICoreBlock_0_Private_1_Subsystem_Components_2_Event_Listener.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Event_Listener/ICoreBlock_0_Private_1_Subsystem_Components_2_Event_Listener.h |
| default size on canvas | 60 × 60 px |
| ports at insert | 0 in, 0 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
The constructor creates no port explicitly — the port list comes from registerInitialPorts (0 in, 0 out) or from the block's configuration.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Event type | Initialize%~%Terminate%~%Reset%~%Reinitialize~~Initialize | EventType |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | built-in/EventListener |
| port-count rule | PortsParam:: |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Event type | EventType | passes through |
Caveat (shown to the user): "Simulink's Event Listener (FEATURES_TO_ADD.md BF25.4): EventType crosses
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
tools/docs/check_block_descriptions.py(P7.1) could not be run when this page was generated, so no verdict is shown. Run it yourself; a page cannot claim an agreement it did not measure.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Event Listener -- makes its subsystem an Initialize, Terminate, Reset or Reinitialize Function Simulink's Event Listener (BlockType=EventListener). It has no ports and computes nothing: ICoreSubsystemControls::eventTypeOf reads its Event type, ICoreSubsystemActivity takes the subsystem out of the step, and ICoreSimulation solves the subsystem's run once -- an Initialize Function before the first output, a Terminate Function after the last step -- while a Reset or Reinitialize Function never runs, as in an R2026a top model.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.