Action Port — Private/Subsystem Components
Private/Subsystem_Components/Action_Port · 0 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Action Port
Control Systems / Ports And Subsystems
Makes the subsystem it sits in an action subsystem: an If or a Switch
Case block chooses, each step, which one of its action subsystems runs.
Simulink’s Action Port block (BlockType=ActionPort), the
one block inside both the If Action Subsystem and the Switch Case Action
Subsystem. To make one, place this block in a subsystem, or insert the ready-made If Action Subsystem or Switch Case Action Subsystem from the library’s Subsystem Templates.
Ports
- Face – placing it inside a subsystem adds an input on the top edge of the subsystem block, labelled Action. Only an output of an If or a Switch Case block may drive it, and each such output drives one action subsystem.
- Output – one, inside the subsystem: the action signal. Leaving it unconnected is fine.
Parameters
- Initialize states – held (default) keeps every state between executions, so a counter inside counts executions, not steps; reset re-seeds them each time the subsystem is chosen again after a step it was not.
Notes
- A subsystem holds at most one. It has to sit inside a subsystem, never at the top level.
- It runs: the subsystem executes on the steps its If or Switch Case chooses it and holds its outputs on the others (Output when disabled on its output gates says held or reset).
Code export
All ten targets: the subsystem's blocks run under a guard that reads this input, so they execute exactly on the steps the If or Switch Case chooses them. Initialize states reset is carried by the six software targets and refused by name on VHDL, Verilog, SystemVerilog and PLC-ST.
Simulink bridge
Both directions, as Simulink’s built-in/ActionPort inside the
subsystem and the subsystem’s Ifaction input on its face, which an If
or Switch Case output drives. Initialize states goes to
InitializeStates, one value for one value. The library’s
If Action Subsystem and Switch Case Action Subsystem import as a
subsystem holding this port, an input and an output, as R2026a makes them.
Simulink’s Action port has no output, so a wire out of this block does not
cross, and the export says so.
Code facts#
| Fact | Value |
|---|---|
| registered type | Private/Subsystem_Components/Action_Port |
| family | Private/Subsystem_Components |
| solver environment class | ICoreBlock_0_Private_1_Subsystem_Components_2_Action_Port |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Action_Port/ICoreBlock_0_Private_1_Subsystem_Components_2_Action_Port.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Private/Subsystem_Components/Action_Port/ICoreBlock_0_Private_1_Subsystem_Components_2_Action_Port.h |
| default size on canvas | 60 × 60 px |
| ports at insert | 0 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
The constructor creates no port explicitly — the port list comes from registerInitialPorts (0 in, 1 out) or from the block's configuration.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Initialize states | held%~%reset~~held | InitializeStates |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | built-in/ActionPort |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Initialize states | InitializeStates | held → held, reset → reset |
Caveat (shown to the user): Simulink's Action port block (built-in/ActionPort) inside the action subsystem, and the subsystem's Ifaction input on the face (FEATURES_TO_ADD.md BF8.5).
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
tools/docs/check_block_descriptions.py(P7.1) could not be run when this page was generated, so no verdict is shown. Run it yourself; a page cannot claim an agreement it did not measure.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.