Transposed Conv 1D — Machine Learning/Neural Networks
Machine_Learning/Neural_Networks/Transposed_Conv_1D · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Transposed Conv 1D
Machine Learning / Neural Networks
The upsampling convolution – torch.nn.ConvTranspose1d.
Each input sample is scattered across the kernel rather than a window
being gathered into one output:
ui contributes wj·ui to output (i·S + j − P), and Lout = (L−1)·S − 2P + K + OP
This is the decoder half of a 1-D autoencoder, and the only way a stack built from these blocks gets back to its input length: with Stride > 1 it lengthens the signal, where Conv 1D shortens it.
It is not a deconvolution. It does not invert a Conv 1D – it only restores the shape that one would have consumed. The values are a fresh learned mapping.
Ports
- u – the sequence, a column [L,1].
- Output – y, a column [Lout,1] as above. The block resizes its output when L or any of the geometry changes.
Parameters
- Kernel – w, the [K,1] taps in signal order.
- Bias – b, one scalar added to every output.
- Stride – S ≥ 1. Here it inserts zeros between inputs rather than skipping outputs, which is what makes the block upsample.
- Padding – P ≥ 0. It trims P entries from each end of the result – the mirror of Conv 1D, where padding adds them.
- Output Padding – OP ≥ 0, appended to the output length. This exists to break a real ambiguity: with S > 1 several input lengths give the same Conv 1D output length, so the inverse shape is not unique and OP picks which one. The appended entries receive no contribution and carry the bias alone – that is the framework behaviour, not a defect.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust,
C, C++, VHDL, Verilog, SystemVerilog and
PLC Structured Text. Which inputs reach which output is decided by a
divisibility condition, and that condition is evaluated at export
time: the emitted code is a plain sum of products per output, with no
modulo, no bounds check and no loop bound anywhere. The kernel and bias are
baked in at full setprecision(17).
The three HDL targets are ordinary Q16.16 fixed point and are offered for synthesis.
Simulink bridge
None. Simulink's transposed convolution exists only inside its Deep
Learning blocks, which take a trained network object. The bridge reports
the block rather than dropping it silently, and it has no parity
testbench, which is the documented consequence of
Support::None.
Notes
- Algebraic and stateless; it maps the current input column, not a history.
- Linear in u, but it carries no state space: an
[Lout,L] feed-through is not what
ICoreStateSpace's merge rules are for. - Single channel, as with Conv 1D: a multi-channel form needs a three-dimensional weight tensor, which a two-dimensional config cannot carry without a flattening convention neither block defines.
- With S > 1 many outputs receive exactly one contribution and the ends may receive none. That is inherent to scattering, not a sign of a mis-sized kernel.
Code facts#
| Fact | Value |
|---|---|
| registered type | Machine_Learning/Neural_Networks/Transposed_Conv_1D |
| family | Machine_Learning/Neural_Networks |
| solver environment class | ICoreBlock_0_Machine_Learning_1_Neural_Networks_2_Transposed_Conv_1D |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Machine_Learning/Neural_Networks/Transposed_Conv_1D/ICoreBlock_0_Machine_Learning_1_Neural_Networks_2_Transposed_Conv_1D.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Machine_Learning/Neural_Networks/Transposed_Conv_1D/ICoreBlock_0_Machine_Learning_1_Neural_Networks_2_Transposed_Conv_1D.h |
| default size on canvas | 128 × 82 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | out | ICoreDouble | y |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Kernel | [0.6; -0.25; 0.9] | — |
Bias | 0.1 | — |
Stride | 2 | — |
Padding | 0 | — |
Output Padding | 0 | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): no Simulink equivalent as a signal block: transposed convolution exists only inside the Deep Learning blocks, which take a trained network OBJECT rather than a kernel, and no config value crosses the bridge as an object
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Transposed Conv 1D — the upsampling convolution, Conv_1D's tap table reversed input i scatters w[j]*u[i] into output (i*S + j - P); Lout = (L-1)*S - 2P + K + OP
Conv_1D gathers a window into one output; this scatters one input across a window. Both resolve every tap at EXPORT time, so neither emits a bounds check — here that also removes a divisibility test, which is the part that would otherwise cost every backend an integer modulo per output.
Genuine Q16.16 on the three HDL targets: multiply-accumulate and nothing else.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 [3x1] entry 0 |
|---|---|---|
| 0 | -2 | [-1.1, 0.6, -1.7] |
| 0.4 | 0.5 | [0.4, -0.025, 0.55] |
| 0.8 | -2 | [-1.1, 0.6, -1.7] |
| 1.2 | 0.5 | [0.4, -0.025, 0.55] |
| 1.6 | -2 | [-1.1, 0.6, -1.7] |
| 2 | 0.5 | [0.4, -0.025, 0.55] |
| 2.4 | -2 | [-1.1, 0.6, -1.7] |
| 2.8 | 0.5 | [0.4, -0.025, 0.55] |
| 3.2 | -2 | [-1.1, 0.6, -1.7] |
| 3.6 | 0.5 | [0.4, -0.025, 0.55] |
| 4 | -2 | [-1.1, 0.6, -1.7] |
| 4.4 | 0.5 | [0.4, -0.025, 0.55] |
| 4.8 | -2 | [-1.1, 0.6, -1.7] |
| 5.2 | 0.5 | [0.4, -0.025, 0.55] |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0.1 … 0.7 |
ramp | Ramp: slope 1 from t = 0 | 0.1 … 3.58 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -0.5 … 0.6997 |
step | Step: 0 -> 1 at t = 1 s | 0.1 … 0.7 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Machine_Learning__Neural_Networks__Transposed_Conv_1D.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).