Generated reference › MLP Network — Machine Learning/Neural Networks
kind: generated#block#machine-learning-neural-networks

MLP Network — Machine Learning/Neural Networks

Machine_Learning/Neural_Networks/MLP_Network · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Description#

The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.

MLP Network

Machine Learning / Neural Networks

A whole multi-layer perceptron in one block, evaluated at inference: h₀ = u, then hₖ = actₖ(Wₖ·hₖ₋₁ + bₖ) for each layer k, and y = hₙ. Each layer is exactly what a Dense_Layer computes, so a trained 2–4 layer stack goes into one block instead of four blocks and three links.

Ports

  • u – the network input, a column [m,1]. m must equal the number of COLUMNS of Weights 1, and it is checked rather than broadcast.
  • Outputy, a column [p,1], where p is the number of ROWS of the LAST used layer's weight matrix. So the network's output shape follows Layers as well as the weights, and the block resizes its output when you change either.

Parameters

  • Layers – how many of the four layer slots the network uses, 1 to 4. The slots past it are ignored entirely: their values are not read, not checked and not exported. This is an explicit count rather than "however many weight boxes you filled in", because an empty config value cannot be read back – see Notes.
  • Weights 1Weights 4Wₖ, the [pₖ,pₖ₋₁] weight matrix of layer k, one row per unit of that layer. This is layer.weight in PyTorch and layer.get_weights()[0].T in Keras – note the transpose: Keras stores it the other way round, and this block wants PyTorch's orientation. The layers must chain: the COLUMNS of Weights k+1 must equal the ROWS of Weights k, which is checked with a message naming both.
  • Bias 1Bias 4bₖ, a [pₖ,1] column, one entry per unit of that layer. For a layer trained with bias=False, give a zero column of the right height rather than an empty value.
  • Activation 1Activation 4 – applied elementwise to that layer's Wₖ·h + bₖ. One combo per layer, carrying the same four choices as Dense_Layer:
    • Linear – none at all. The usual choice for the LAST layer of a regression network.
    • ReLU – max(0, v). The usual hidden-layer choice.
    • Tanh – squashes to (−1, 1).
    • Sigmoid – 1 ÷ (1 + e−v), squashes to (0, 1); a single-unit last layer with this is a binary classifier's head.
  • Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Every weight and bias is baked into the generated code as a literal at full setprecision(17), so the exported network is bit-comparable with the in-app run; there is no tunable parameter, because a trained weight is not something to retune on the target.

The whole network is unrolled at export time – no weight array, no loop bound and no index arithmetic appears in any target. The seven software targets carry each layer's units in named locals, so the emitted code grows with the SUM of the layer widths.

The three HDL targets are simulation-only: they carry the network in real arithmetic and quantize only at the port boundary. Tanh and Sigmoid are transcendental and have no place in a Q16.16 datapath, and a network whose synthesizability depended on which activations you picked would be worse than one that says plainly that none of the three is offered for synthesis. ⚠ A VHDL block body cannot declare a real variable, so the three HDL targets inline the layers instead of naming them, and their emitted expression grows with the PRODUCT of the layer widths rather than the sum. Four wide layers is a large expression; it is correct, and it is a reason to keep an HDL-targeted network narrow.

Simulink bridge

None. Simulink's Deep Learning blocks take a trained network object, not a set of matrices, and no config value can carry an object across the bridge – so there is nothing this block could be mapped to that would survive the trip. The bridge reports it rather than dropping it silently, and it has no parity testbench, which is the documented consequence of Support::None rather than a gap. Code export verification still covers it across all ten languages.

Notes

  • Algebraic and stateless: the output depends only on the current input, so the network cannot break an algebraic loop.
  • No state space, deliberately. Each bias makes its layer affine rather than linear, and three of the four activations are nonlinear, so a stored A/B/C/D would be true in at most one configuration. Model reduction reports the block as unmergeable, which is the honest answer.
  • Why Layers is a number and not an empty box. A config left empty is typed as a string, not as an empty matrix, so it is filed where matrix configs are not; reading it back does not return something empty, it stops the run. A block also cannot ask whether a config is there before reading it. So the four slots always hold real values and Layers says how many are used. The shipped defaults chain, which means raising Layers is valid with no other edit.
  • The network is a column map: u is [m,1] and y is [p,1]. Feed a batch one sample at a time.

Code facts#

FactValue
registered typeMachine_Learning/Neural_Networks/MLP_Network
familyMachine_Learning/Neural_Networks
solver environment classICoreBlock_0_Machine_Learning_1_Neural_Networks_2_MLP_Network
sourcesrc/ICoreSDK/ICoreBlockLibrary/Blocks/Machine_Learning/Neural_Networks/MLP_Network/ICoreBlock_0_Machine_Learning_1_Neural_Networks_2_MLP_Network.cpp
headersrc/ICoreSDK/ICoreBlockLibrary/Blocks/Machine_Learning/Neural_Networks/MLP_Network/ICoreBlock_0_Machine_Learning_1_Neural_Networks_2_MLP_Network.h
default size on canvas130 × 100 px
ports at insert1 in, 1 out
code generators implementedPython, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Ports#

#DirectionSignal typeDescription label
1inICoreDoubleu
2outICoreDoubley

Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.

Configuration variables#

Config variableDefaultSimulink parameter
Layers2
impl->weightsKey(k) (unresolved)defW[static_cast<size_t>(k)]
impl->biasKey(k) (unresolved)defB[static_cast<size_t>(k)]
impl->activationKey(k) (unresolved)actOptionsdefAct[static_cast<size_t>(k)]

Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.

supportSupport::None
Simulink path
port-count rulePortsParam::None
SampleTime parameteryes

Caveat (shown to the user): no Simulink equivalent that could carry the weights: its Deep Learning blocks take a trained network OBJECT rather than weight matrices, and no config value crosses the bridge as an object. Re-create the network on the Simulink side and paste the same weights and biases in

Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h

Description vs code#

The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:

  • B0 config name(s) this tool cannot resolve: impl->weightsKey(k), impl->biasKey(k), impl->activationKey(k)
  • B0 every stimulus in the sample errored — cross-checks skipped

The verdict above is tools/docs/check_block_descriptions.py (P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.

File banner (developer view)#

The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).

MLP Network — a whole multi-layer perceptron in one block, evaluated at inference h0 = u, hk = act_k(Wk*h(k-1) + bk) k = 1..n, y = hn

This is Dense_Layer applied n times. The weights are CONFIG, not a file, for the reason that makes this whole family verifiable (see the header), and the depth is an explicit "Layers" count rather than a count of non-empty configs -- the header explains why the CODE forbids the latter, which is the one design decision on this block that is not a matter of taste.

The three HDL targets are SIMULATION-ONLY, exactly as Dense_Layer's are and for the same reason: Tanh and Sigmoid are transcendental and have no place in a Q16.16 datapath. A network whose synthesizability depended on which activations you picked would be worse than one that says plainly that none of the three is offered for synthesis.

Sample results#

No stimulus produced a sampled output in this rig — Invalid input size at: ICore Blocks/Home/MLP Network. That is a fact about the single-block rig, not a verdict on the block: an offline batch fit, a block whose output only appears at onSolverFinish, or one that needs a driven environment cannot be exercised alone.

Category unsampled · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60

Sample data: docs/generated/samples/Machine_Learning__Neural_Networks__MLP_Network.json