Triangular Pulse — Control Systems/Waveform Functions
Control_Systems/Waveform_Functions/Triangular_Pulse · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Triangular Pulse
Control Systems / Waveform Functions
One aperiodic unit-height triangle of width W spanning (−W/2, +W/2), with its apex placed by a skew S, evaluated entry by entry. The apex sits at xa = (W/2)·S, and
- rising side: y = (2x + W) / (W + W·S) for −W/2 < x < xa
- falling side: y = (W − 2x) / (W − W·S) for xa < x < +W/2
- y = 1 at x = xa, and y = 0 outside the span
This is the triangle function, not a generator: the argument arrives on the input port and the block has no clock of its own. For a repeating ramp use Control Systems / Sources / Signal Generator in its sawtooth mode.
Ports
- Input – the argument x of the relations above, of any size [m,n], applied entry by entry. It shares the unit of the width.
- Output – the result y, of the SAME size [m,n], in [0,1]. The block never reshapes a signal.
Parameters
- Pulse Width (s) – the width W, a positive scalar. The triangle spans (−W/2, +W/2); a non-scalar or non-positive width is reported and stops the run. Default 1.
- Skew – the apex position S, a scalar in [−1, +1]. 0 is the symmetric triangle, +1 places the apex on the right edge (a pure rising ramp) and −1 on the left edge (a pure falling ramp). A value outside the range is reported and stops the run. Default 0.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text.
The width and the skew are structural, so the half width, the apex position and the two divisors are computed once at export time and written into the body as decimal literals; the generated core carries no tunable parameter. Re-export after changing either value.
The three HDL targets are simulation-only. The apex is found by an
exact comparison, which has no meaning once the argument has been rounded onto
the Q16.16 grid, so those cores convert at the port boundary and compare in
real arithmetic instead. Correct in simulation, and not offered as
synthesizable.
Simulink bridge
None. The Simulink standard library has no aperiodic triangle block:
MathWorks offers it as the Signal Processing Toolbox function
tripuls, which is not a block and has no library path a diagram
could name. A model carrying this block is reported rather than silently dropped
when it crosses, and none of its configuration crosses either – "Pulse
Width (s)", "Skew" and "Sampling Time (s)" have no counterparts to be written
to.
Notes
- Algebraic, with no state: the output depends only on the current input.
- Not linear. Piecewise linear is not linear: no single A/B/C/D covers the two ramps and the two flat regions, so the block deliberately carries no state space and model reduction reports it as unmergeable.
- At S = ±1 one of the two divisors is zero, and the division that would use it is unreachable – with S = +1 the falling test needs x > W/2 and x < W/2 at once. The four cases are tested in the same order in every generated core so that stays true after export.
- The span is open at both ends: the two edges evaluate to 0, and the value approaches 0 continuously from inside, so the pulse has no jump.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Waveform_Functions/Triangular_Pulse |
| family | Control_Systems/Waveform_Functions |
| solver environment class | ICoreBlock_0_Control_Systems_1_Waveform_Functions_2_Triangular_Pulse |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Waveform_Functions/Triangular_Pulse/ICoreBlock_0_Control_Systems_1_Waveform_Functions_2_Triangular_Pulse.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Waveform_Functions/Triangular_Pulse/ICoreBlock_0_Control_Systems_1_Waveform_Functions_2_Triangular_Pulse.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Pulse Width (s) | 1 | — |
Skew | 0 | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): the aperiodic triangle is a Signal Processing Toolbox FUNCTION (tripuls), not a Simulink library block, so there is no path a diagram could name; the block is reported rather than dropped when a model crosses
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Triangular Pulse -- one unit-height triangle of width W, apex placed by a skew S Four cases, tested in this order in every one of the ten generated cores: rising side, falling side, the apex itself, and everything outside the span. The ORDER is load bearing, not stylistic -- at S = +1 or S = -1 one of the two divisors is zero, and it is only the earlier tests failing that keeps the division that would use it unreachable.
Every constant the four cases need is computed once in double arithmetic HERE and embedded in each core as a decimal literal: the half width, the apex position, the width itself and the two divisors. No target re-derives them, so no two targets disagree about where the apex is.
The three hardware-description targets evaluate in floating point and are offered as simulation-only. The apex is found by an EXACT comparison, and an exact comparison has no meaning once the argument has been rounded onto the Q16.16 grid -- so those cores convert at the port boundary and compare in floating point instead.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | 0 |
| 0.4 | 0.5 | 0 |
| 0.8 | -2 | 0 |
| 1.2 | 0.5 | 0 |
| 1.6 | -2 | 0 |
| 2 | 0.5 | 0 |
| 2.4 | -2 | 0 |
| 2.8 | 0.5 | 0 |
| 3.2 | -2 | 0 |
| 3.6 | 0.5 | 0 |
| 4 | -2 | 0 |
| 4.4 | 0.5 | 0 |
| 4.8 | -2 | 0 |
| 5.2 | 0.5 | 0 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 1 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 0 … 1 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit 87d3936094fa2ff37688c80c5846c4dd08d6a27d · produced by docsSample --out <folder> --blocks Sinc Rectangular_Pulse Triangular_Pulse Gaussian_Monopulse Gaussian_RF_Pulse Dirichlet_Function --steps 60 · data docs/generated/samples/Control_Systems__Waveform_Functions__Triangular_Pulse.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).