Rectangular Pulse — Control Systems/Waveform Functions
Control_Systems/Waveform_Functions/Rectangular_Pulse · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Rectangular Pulse
Control Systems / Waveform Functions
One aperiodic unit-height rectangle of width W centred on the origin, evaluated entry by entry: y = 1 on the half-open interval [−W/2, +W/2) and y = 0 everywhere else.
This is the rectangle function, not a pulse generator: the argument arrives on the input port and the block has no clock of its own. Drive it from a clock to place one pulse around t = 0, and shift the clock to place it elsewhere. For a periodic train use Control Systems / Sources / Pulse Generator.
Ports
- Input – the argument x of the relation above, of any size [m,n], applied entry by entry. It shares the unit of the width.
- Output – the result y, of the SAME size [m,n], and always either 0 or 1. The block never reshapes a signal.
Parameters
- Pulse Width (s) – the width W, a positive scalar. The pulse spans −W/2, +W/2); a non-scalar or non-positive width is reported and stops the run. Default 1.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text.
The width is a structural value, so both edge thresholds are computed once at export time and written into the body as decimal literals; the generated core carries no tunable parameter. Re-export after changing the width.
The three HDL targets are simulation-only. The interval is defined to
within one double epsilon, which is fourteen orders of magnitude finer than one
Q16.16 quantum, so neither the half-open right edge nor the closed left edge has
a fixed-point meaning; the generated cores convert at the port boundary and
compare in real arithmetic instead. Correct in simulation, and not
offered as synthesizable.
Simulink bridge
None. The Simulink standard library has no aperiodic rectangle block:
MathWorks offers it as the Signal Processing Toolbox function
rectpuls, which is not a block and has no library path a diagram
could name, and Pulse Generator is a periodic train rather than a single pulse.
A model carrying this block is reported rather than silently dropped when it
crosses, and no configuration of it crosses either – neither "Pulse Width
(s)" nor "Sampling Time (s)" has a counterpart to be written to.
Notes
- Algebraic, with no state: the output depends only on the current input.
- Not linear – it is the archetypal discontinuity – so the block deliberately carries no state space and model reduction reports it as unmergeable.
- The interval is half-open on purpose. The left edge is inside the pulse and the right edge is outside it, so exactly one sample lands on the rising edge however finely the argument is swept, and a train assembled from shifted copies neither overlaps nor gaps.
- Both edges are decided with an absolute tolerance of one double epsilon, so a width and an argument that were each computed rather than typed still land where the arithmetic says they should.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Waveform_Functions/Rectangular_Pulse |
| family | Control_Systems/Waveform_Functions |
| solver environment class | ICoreBlock_0_Control_Systems_1_Waveform_Functions_2_Rectangular_Pulse |
| source | [src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Waveform_Functions/Rectangular_Pulse/ICoreBlock_0_Control_Systems_1_Waveform_Functions_2_Rectangular_Pulse.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Waveform_Functions/Rectangular_Pulse/ICoreBlock_0_Control_Systems_1_Waveform_Functions_2_Rectangular_Pulse.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Pulse Width (s) | 1 | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): the aperiodic rectangle is a Signal Processing Toolbox FUNCTION (rectpuls), not a Simulink library block, so there is no path a diagram could name; Pulse Generator is a periodic train and not the same thing, and the block is reported rather than dropped when a model crosses
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Rectangular Pulse -- one unit-height rectangle of width W, centred on x = 0 y = 1 on [-W/2, +W/2) and y = 0 elsewhere, entry by entry. Algebraic and stateless. No state space -- see the header for why.
Both edge decisions are precomputed in double arithmetic HERE and embedded in every generated core as decimal literals, so no target re-derives W/2 or subtracts the tolerance for itself: ten backends that each compute the threshold their own way would disagree on the one sample that lands nearest to it, which is exactly the sample this block exists to place.
The three hardware-description targets evaluate in floating point and are offered as simulation-only. The reason is the tolerance rather than the rectangle: the interval is defined to within one double epsilon, which is fourteen orders of magnitude below one Q16.16 quantum, so the half-open edge and the closed left edge have no fixed-point meaning at all. They also spell the comparison as a pair of inequalities rather than through an absolute value, because Verilog's real system functions do not include one.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | 0 |
| 0.4 | 0.5 | 0 |
| 0.8 | -2 | 0 |
| 1.2 | 0.5 | 0 |
| 1.6 | -2 | 0 |
| 2 | 0.5 | 0 |
| 2.4 | -2 | 0 |
| 2.8 | 0.5 | 0 |
| 3.2 | -2 | 0 |
| 3.6 | 0.5 | 0 |
| 4 | -2 | 0 |
| 4.4 | 0.5 | 0 |
| 4.8 | -2 | 0 |
| 5.2 | 0.5 | 0 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 1 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 0 … 1 |
step | Step: 0 -> 1 at t = 1 s | 0 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit 87d3936094fa2ff37688c80c5846c4dd08d6a27d · produced by docsSample --out <folder> --blocks Sinc Rectangular_Pulse Triangular_Pulse Gaussian_Monopulse Gaussian_RF_Pulse Dirichlet_Function --steps 60 · data docs/generated/samples/Control_Systems__Waveform_Functions__Rectangular_Pulse.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).