Atan2 — Control Systems/Trigonometry
Control_Systems/Trigonometry/Atan2 · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Atan2
Control Systems / Trigonometry
Outputs the four-quadrant arctangent of u₁/u₂, in radians and in (−π, π] – the angle of the point (u₂, u₁), using the signs of BOTH operands to place the quadrant: y = atan2(u₁, u₂).
Defined for every pair, including u₂ = 0; at the origin it is 0.
Ports
- u1 – the numerator (the "y" operand), of any size [m,n].
- u2 – the denominator (the "x" operand). Either the SAME size [m,n] as u1, or a scalar [1,1], which is then applied to every entry of u1. Any other size is an error rather than a guess.
- Output – the angle y, the SAME size [m,n] as u1. The block never reshapes a signal.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. There is nothing to tune, so nothing is exposed as a parameter on the generated core.
The seven software targets agree exactly, and at a pole or out of domain they all produce the same IEEE NaN or ±Inf.
The three HDL targets are simulation-only. There is no fixed-point
atan2 in the Q16.16 datapath to call, so the generated cores convert at the port
boundary and evaluate in real arithmetic – correct in
simulation, but not offered as synthesizable. They carry neither NaN nor infinity, so out of domain they answer 0 where the software targets answer NaN or ±Inf, and PLC Structured Text answers 0 there too rather than dividing by zero at run time.
Simulink bridge
Export only, to simulink/Math Operations/Trigonometric
Function with Operator fixed at atan2. The block has
no parameters of its own, so besides that operator the only pair is the global
one: "Sampling Time (s)" to SampleTime, as on every block. Three
further parameters are always written out because this block offers no choice
behind them – ApproximationMethod is None, which
pins Simulink to the exact library function rather than its CORDIC or lookup
approximation; OutputSignalType is real; and
AngleUnit is radian.
Why export only. Import of that Simulink block belongs to Control Systems / Base Blocks / Trigonometric Function, which carries the operator as a config variable and so can represent all thirteen. If this block claimed the import as well, two ICore types would answer to one Simulink path and which of them an imported model resolved to would depend on link order. Exporting is unambiguous in the other direction, because it starts from the ICore type.
Notes
- Algebraic, with no state: the output depends only on the current input.
- Not linear, so the block deliberately carries no state space and model reduction reports it as unmergeable.
- The only block of this family with two inputs.
- atan2(0, 0) is 0 in C, MATLAB and every software target here. VHDL's
ARCTAN(Y, X)asserts on that pair rather than returning a value, so the three HDL targets guard it and answer 0.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Trigonometry/Atan2 |
| family | Control_Systems/Trigonometry |
| solver environment class | ICoreBlock_0_Control_Systems_1_Trigonometry_2_Atan2 |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Trigonometry/Atan2/ICoreBlock_0_Control_Systems_1_Trigonometry_2_Atan2.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Trigonometry/Atan2/ICoreBlock_0_Control_Systems_1_Trigonometry_2_Atan2.h |
| default size on canvas | 80 × 70 px |
| ports at insert | 2 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u1 |
| 2 | in | ICoreDouble | u2 |
| 3 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::ExportOnly |
| Simulink path | simulink/Math Operations/Trigonometric Function |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| always set | Operator = atan2, ApproximationMethod = None, OutputSignalType = real, AngleUnit = radian |
Caveat (shown to the user): exports to Simulink's Trigonometric Function with Operator fixed at 'atan2'. IMPORT of that block belongs to Base_Blocks/Trigonometric_Function, which carries the operator as a config variable and so can represent all thirteen -- two ICore types answering to one Simulink path would make an imported model resolve by link order
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Atan2 -- y = atan2(u1, u2) One function, fixed, and the only BINARY block of this family.
Algebraic and stateless. No state space -- see the header for why.
Both operands cross to every backend, and the origin is guarded in the three HDLs and in PLC ST: VHDL's math_real ARCTAN(Y, X) ASSERTS on (0, 0) rather than returning a value, which would abort the simulation.
Sample results#
| t | in ICoreDouble-Out-0 | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|---|
| 0 | -2 | -2 | -2.356 |
| 0.4 | 0.5 | 0.5 | 0.7854 |
| 0.8 | -2 | -2 | -2.356 |
| 1.2 | 0.5 | 0.5 | 0.7854 |
| 1.6 | -2 | -2 | -2.356 |
| 2 | 0.5 | 0.5 | 0.7854 |
| 2.4 | -2 | -2 | -2.356 |
| 2.8 | 0.5 | 0.5 | 0.7854 |
| 3.2 | -2 | -2 | -2.356 |
| 3.6 | 0.5 | 0.5 | 0.7854 |
| 4 | -2 | -2 | -2.356 |
| 4.4 | 0.5 | 0.5 | 0.7854 |
| 4.8 | -2 | -2 | -2.356 |
| 5.2 | 0.5 | 0.5 | 0.7854 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 0.7854 |
ramp | Ramp: slope 1 from t = 0 | 0 … 0.7854 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -2.356 … 0.7854 |
step | Step: 0 -> 1 at t = 1 s | 0 … 0.7854 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Trigonometry__Atan2.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).