Asinh — Control Systems/Trigonometry
Control_Systems/Trigonometry/Asinh · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Asinh
Control Systems / Trigonometry
Outputs the inverse hyperbolic sine of the input: y = asinh(u) = ln(u + √(u² + 1)), applied entry by entry, so a matrix signal is transformed element for element.
Defined for every real input.
Ports
- Input – the signal u, of any size [m,n], applied entry by entry.
- Output – the result y, of the SAME size [m,n]. The block never reshapes a signal.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. There is nothing to tune, so nothing is exposed as a parameter on the generated core.
The seven software targets agree exactly, including out of domain, where they all produce IEEE NaN or ±Inf. Two of them lack this function entirely – Java and PLC Structured Text – and build it from logarithms; the other five call the library function, which is more accurate near zero than the logarithmic form.
The three HDL targets are simulation-only. There is no fixed-point
asinh in the Q16.16 datapath to call, so the generated cores convert at the port
boundary and evaluate in real arithmetic – correct in
simulation, but not offered as synthesizable.
Simulink bridge
Export only, to simulink/Math Operations/Trigonometric
Function with Operator fixed at asinh. The block has
no parameters of its own, so besides that operator the only pair is the global
one: "Sampling Time (s)" to SampleTime, as on every block. Three
further parameters are always written out because this block offers no choice
behind them – ApproximationMethod is None, which
pins Simulink to the exact library function rather than its CORDIC or lookup
approximation; OutputSignalType is real; and
AngleUnit is radian.
Why export only. Import of that Simulink block belongs to Control Systems / Base Blocks / Trigonometric Function, which carries the operator as a config variable and so can represent all thirteen. If this block claimed the import as well, two ICore types would answer to one Simulink path and which of them an imported model resolved to would depend on link order. Exporting is unambiguous in the other direction, because it starts from the ICore type.
Notes
- Algebraic, with no state: the output depends only on the current input.
- Not linear, so the block deliberately carries no state space and model reduction reports it as unmergeable.
- Odd, and asinh(0) = 0.
- Grows like ln(2u) for large u, so it is the gentlest of the four inverse hyperbolics.
- Java and PLC Structured Text have no asinh and rebuild it from the logarithm above; the other five call their library function, which is more accurate near zero (the logarithmic form loses significance to cancellation there).
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Trigonometry/Asinh |
| family | Control_Systems/Trigonometry |
| solver environment class | ICoreBlock_0_Control_Systems_1_Trigonometry_2_Asinh |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Trigonometry/Asinh/ICoreBlock_0_Control_Systems_1_Trigonometry_2_Asinh.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Trigonometry/Asinh/ICoreBlock_0_Control_Systems_1_Trigonometry_2_Asinh.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::ExportOnly |
| Simulink path | simulink/Math Operations/Trigonometric Function |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| always set | Operator = asinh, ApproximationMethod = None, OutputSignalType = real, AngleUnit = radian |
Caveat (shown to the user): exports to Simulink's Trigonometric Function with Operator fixed at 'asinh'. IMPORT of that block belongs to Base_Blocks/Trigonometric_Function, which carries the operator as a config variable and so can represent all thirteen -- two ICore types answering to one Simulink path would make an imported model resolve by link order
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Asinh -- y = asinh(u) = ln(u + sqrt(u^2 + 1)) One function, fixed: the block IS y = asinh(u) = ln(u + sqrt(u^2 + 1)).
Algebraic and stateless. No state space -- see the header for why.
Every target calls its own library function rather than rebuilding the maths, with the two exceptions the family shares: Java and IEC Structured Text have no inverse hyperbolics and build those from logarithms.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | -1.444 |
| 0.4 | 0.5 | 0.4812 |
| 0.8 | -2 | -1.444 |
| 1.2 | 0.5 | 0.4812 |
| 1.6 | -2 | -1.444 |
| 2 | 0.5 | 0.4812 |
| 2.4 | -2 | -1.444 |
| 2.8 | 0.5 | 0.4812 |
| 3.2 | -2 | -1.444 |
| 3.6 | 0.5 | 0.4812 |
| 4 | -2 | -1.444 |
| 4.4 | 0.5 | 0.4812 |
| 4.8 | -2 | -1.444 |
| 5.2 | 0.5 | 0.4812 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 0.8814 |
ramp | Ramp: slope 1 from t = 0 | 0 … 2.458 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -0.8814 … 0.8811 |
step | Step: 0 -> 1 at t = 1 s | 0 … 0.8814 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Trigonometry__Asinh.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).