Bit Reverse Order — Control Systems/Transforms
Control_Systems/Transforms/Bit_Reverse_Order · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Bit-Reverse Order
Control Systems / Transforms
Permutes a window into bit-reversed order – the shuffle a decimation-in-time FFT wants on its input, and the one a decimation-in-frequency FFT leaves on its output. Writing rev(k) for the log₂(N) bits of k read backwards:
y[k] = u[rev(k)].
The map is its own inverse: reversing a bit pattern twice returns it, so the same block undoes itself and no direction option is offered.
Ports
- u – the window to shuffle, [N,1] or [1,N], with N a power of two of at least 2.
- y – the shuffled window, the same size and the same orientation as u. A column comes back a column.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It is the block's only parameter: the shuffle follows from the window length and has nothing to tune.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The permutation follows from N alone and is resolved before the run starts, so every target emits it as a fixed list of copies – no bit arithmetic is performed at run time in any of them.
The three HDL targets are fully synthesizable and exact, not
simulation-only: a constant shuffle is wiring. No value is converted to
real on the way through, so the Q-format word arrives at the output
bit for bit.
Simulink bridge
No equivalent, so nothing crosses in either direction.
bitrevorder and digitrevorder are Signal Processing
Toolbox MATLAB functions with no Simulink block behind them, and the DSP System
Toolbox's transform library – FFT, IFFT, Magnitude FFT, DCT, IDCT, the two
cepstra, the two wavelet transforms, Analytic Signal, the two Short-Time FFTs
and Zoom FFT – has none either, because its FFT block does the reordering
internally rather than exposing it. A Simulink model that needs the shuffle on
its own builds it from a Selector.
Notes
- Algebraic and stateless: the output depends only on the window presented this step.
- No state space. A permutation is a genuine D matrix, but one of N² entries carrying no dynamics at all, and every target already emits the copies directly.
- A window whose length is not a power of two stops the run with a message naming the length. It is deliberately not zero-padded: padding changes log₂(N), which moves every element rather than only the ones added.
- This is the radix-2 case. MATLAB's
digitrevordergeneralises it to other radices; this block does not offer that, and a model needing it is doing something the FFT family does not.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Transforms/Bit_Reverse_Order |
| family | Control_Systems/Transforms |
| solver environment class | ICoreBlock_0_Control_Systems_1_Transforms_2_Bit_Reverse_Order |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Transforms/Bit_Reverse_Order/ICoreBlock_0_Control_Systems_1_Transforms_2_Bit_Reverse_Order.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Transforms/Bit_Reverse_Order/ICoreBlock_0_Control_Systems_1_Transforms_2_Bit_Reverse_Order.h |
| default size on canvas | 120 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | out | ICoreDouble | y |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): no Simulink equivalent. bitrevorder is a Signal Processing Toolbox MATLAB function, not a block, and the DSP System Toolbox's FFT does its reordering internally rather than exposing it as a block. A Simulink model that needs the shuffle on its own builds it from a Selector
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0every stimulus in the sample errored — cross-checks skipped
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Bit-Reverse Order -- permute a window into bit-reversed order (MATLAB bitrevorder) y[k] = u[rev(k)] rev(k) = the log2(N) bits of k, read backwards
The shuffle a decimation-in-time FFT wants on its input, and the one a decimation-in- frequency FFT leaves on its output. Measured against R2026a: bitrevorder([3 -1 4 1 -5 9 2 -6]) is [3 -5 4 2 -1 9 1 -6].
⚠ IT IS ITS OWN INVERSE -- reversing a bit pattern twice returns it -- so this block has no direction option, and one would be a lie if it did. That is the property the FFT relies on.
⚠ N MUST BE A POWER OF TWO. Rejected rather than zero-padded when it is not, and MATLAB is stricter still (bitrevorder errors out). Padding would be the worst of the three: it changes log2(N), which moves EVERY element rather than just the ones added.
The permutation depends only on N, settled before the run starts, so every backend emits it as a fixed list of copies with no bit arithmetic per sample -- which is also why the three HDL targets are fully synthesizable and exact.
Algebraic and stateless. No state space, for the reason the block beside it gives: a permutation is a genuine D of N^2 entries carrying no dynamics.
Sample results#
No stimulus produced a sampled output in this rig — Invalid window length at: ICore Blocks/Home/Bit Reverse Order. That is a fact about the single-block rig, not a verdict on the block: an offline batch fit, a block whose output only appears at onSolverFinish, or one that needs a driven environment cannot be exercised alone.
Category unsampled · sample time 0.1 · 60 steps · commit 2b8440534 · produced by docsSample --out <folder> --blocks FFT_Shift Bit_Reverse_Order Walsh_Hadamard_Transform Goertzel --steps 60
Sample data: docs/generated/samples/Control_Systems__Transforms__Bit_Reverse_Order.json