String Concatenate — Control Systems/Strings
Control_Systems/Strings/String_Concatenate · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
String Concatenate
Control Systems / Strings
Joins the incoming pieces of text into one, in port order: y = u1 u2 … uN, with nothing inserted between them. Add a separator by wiring a String Constant in as one of the inputs.
Ports
- Inputs – pieces of text (
str,ICoreString), joined top to bottom: two by default, and the count is user-editable. Every one of them carries text, which is not a choice: you pick how many inputs there are, never what they carry. - Output – the joined text (
str,ICoreString), one value.
Parameters
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
The 256-byte limit
A text signal holds at most 256 bytes, so a join longer than that is cut at 256. The cut is counted in bytes, and it can land in the middle of an accented or non-Latin character.
That matters in one place and it is worth knowing about: C and C++ keep the raw bytes of a half-finished character, while Java, Python, MATLAB and Rust cannot hold one and each drops or replaces it. So a join that both exceeds 256 bytes AND is cut inside a multi-byte character is the one case where two exported targets can differ. Text under the limit, or plain English text of any length, is identical everywhere.
Code export
C, C++, Python, MATLAB, Java and Rust all join the same text and cut at the same 256 bytes.
VHDL, Verilog and SystemVerilog do not carry text, and PLC Structured Text is not supported either: the language has a string type, but the check that runs an exported core cannot read one back. An export to any of these four stops and names this block and the reason.
Simulink bridge
Import and export, mapped to simulink/String/String Concatenate. The
number of inputs crosses as Inputs. The Simulink block has no
sampling-time setting of its own, so a positive Sampling Time (s) stays
on this side and is reported rather than written.
Notes
- Algebraic, with no state: the output depends only on the current inputs.
- An unconnected input is empty text and contributes nothing, so removing a wire shortens the result rather than breaking it.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Strings/String_Concatenate |
| family | Control_Systems/Strings |
| solver environment class | ICoreBlock_0_Control_Systems_1_Strings_2_String_Concatenate |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Strings/String_Concatenate/ICoreBlock_0_Control_Systems_1_Strings_2_String_Concatenate.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Strings/String_Concatenate/ICoreBlock_0_Control_Systems_1_Strings_2_String_Concatenate.h |
| default size on canvas | 90 × 70 px |
| ports at insert | 2 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++ |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreString | — |
| 2 | in | ICoreString | — |
| 3 | out | ICoreString | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/String/String Concatenate |
| port-count rule | PortsParam::MuxCount |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
Caveat (shown to the user): "the input count crosses as Inputs
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
String Concatenate -- text in, one longer piece of text out y = u1 + u2 + ... + uN, cut at ICORE_STRING_CAPACITY bytes. A variable number of String inputs; one String output. Like String Constant, the value leaves through the PORT rather than through compute_h's return, because a String port's matrix is a placeholder (D2).
It is the second block, with String Constant, that a String signal can come OUT of -- and the only one that can make a long one, which is why the capacity cut lives here in practice even though the rule belongs to the port.
Sample results#
This block carries a ICoreString signal, whose value is text rather than a number and is not something a plot has an axis for. The samples are in the table below, exactly as the run recorded them.
| t | in ICoreString-Out-0 | in ICoreString-Out-0 | out ICoreString-Out-0 |
|---|---|---|---|
| 0 | u0 | u1 | u0u1 |
| 0.4 | u0 | u1 | u0u1 |
| 0.8 | u0 | u1 | u0u1 |
| 1.2 | u0 | u1 | u0u1 |
| 1.6 | u0 | u1 | u0u1 |
| 2 | u0 | u1 | u0u1 |
| 2.4 | u0 | u1 | u0u1 |
| 2.8 | u0 | u1 | u0u1 |
| 3.2 | u0 | u1 | u0u1 |
| 3.6 | u0 | u1 | u0u1 |
| 4 | u0 | u1 | u0u1 |
| 4.4 | u0 | u1 | u0u1 |
| 4.8 | u0 | u1 | u0u1 |
| 5.2 | u0 | u1 | u0u1 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | — |
ramp | Ramp: slope 1 from t = 0 | — |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | — |
step | Step: 0 -> 1 at t = 1 s | — |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit 6280f52f3 · produced by docsSample --out <folder> --blocks Rational_Resample,Three_Axis_Accelerometer,Three_Axis_Gyroscope,Three_Axis_Inertial_Measurement_Unit,Eclipse_Shadow_Model,To_String,String_To_ASCII,ASCII_To_String,Substring,String_Constant,String_Concatenate,String_Compare,String_Length --steps 60 · data docs/generated/samples/Control_Systems__Strings__String_Concatenate.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).