Decibel Conversion — Control Systems/Spectral Measurements

Control_Systems/Spectral_Measurements/Decibel_Conversion · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Description#

The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.

Code facts#

Ports#

Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.

Configuration variables#

Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.

Simulink bridge#

Caveat (shown to the user): maps to the DSP System Toolbox's dB Conversion, simulated over all sixteen combinations of its four parameters and reproduced exactly. ONLY THE TWO FORWARD MODES CROSS: the Simulink block converts to decibels and has no inverse, so "dB to Amplitude" and "dB to Power" have no counterpart and are reported rather than translated. Two measured details worth carrying: the load resistance is IGNORED in the Power direction on both sides, and the block has no SampleTime parameter, so an explicit rate does not cross the bridge. Note dspmathops/dB Gain is a different block (a gain expressed in decibels) and is not this one

Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h

Description vs code#

The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.

The verdict above is tools/docs/check_block_descriptions.py (P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.

File banner (developer view)#

The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).

Decibel Conversion -- the five MATLAB decibel functions as one elementwise block Amplitude to dB y = 10*log10(a*a / R) [+30 for dBm] db, mag2db Power to dB y = 10*log10(a) [+30 for dBm] pow2db dB to Amplitude y = sqrt(R * 10^((u [-30]) / 10)) db2mag dB to Power y = 10^((u [-30]) / 10) db2pow

a is the input, or the input plus one machine epsilon when the log-of-zero guard is on.

⚠ EVERYTHING BELOW WAS SIMULATED IN R2026a, NOT READ OFF A PAGE. dspmathops/dB Conversion was driven with [0.25 0.5 1 2 4 10 0.001 100] over all sixteen combinations of its four parameters, and then with [-2 -0.5 0 0.5 2 -1e-8] to find the edges. Three facts came out of that and each of them is a way to be wrong:

1. THE TWO DIRECTIONS ARE NOT SYMMETRIC ABOUT ZERO. Amplitude squares before the logarithm,

so -2 gives the same +6.02 dB as +2. Power does NOT: it takes the log of the input, so a negative input is NaN and a zero is -Inf, and Simulink prints "Log of a negative number" rather than refusing. Writing Amplitude as 20*log10(u) -- the form mag2db uses, and the one a reader reaches for -- would give NaN on half of any zero-mean signal.

1. THE LOAD RESISTANCE IS IGNORED IN THE POWER DIRECTION. R = 1 and R = 50 give the same

numbers to the last bit there. A power is already a power; only an amplitude needs a resistance to become one.

1. THE GUARD ADDS eps TO THE INPUT, NOT TO THE LOGARITHM'S ARGUMENT. Measured at u = 0:

Amplitude gives -313.07 dB, which is 10*log10(eps*eps) and not 10*log10(eps); Power gives -156.54, which is 10*log10(eps). So the addition happens once, before the square.

TWO OF THE FOUR MODES CROSS AND TWO CANNOT: Simulink's block is the forward pair and has no inverse. The catalog maps the two forward values of the mode and leaves the two inverse ones unmapped, which the exporter REPORTS rather than translating into something wrong.

⚠ THE THREE HDL TARGETS ARE SIMULATION-ONLY real ARITHMETIC, quantizing only at the port boundary -- the same choice Recursive IIR makes and for a sharper reason: a logarithm has no Q16.16 form at all, and the answer's range is unbounded below (a zero input is -Inf before the guard and -313 dB after it). VHDL gets LOG10/EXP from ieee.math_real; Verilog and SystemVerilog get $log10/$exp. 10^x is emitted as exp(x*ln10) rather than as a power operator, because that spelling exists in all three.

ALGEBRAIC and elementwise: the output has the input's shape, one step is one conversion and nothing is held between samples. No state space -- a logarithm is not y = D*u.

Sample results#

8 sample(s) were non-finite (nan/inf) and are absent from the plot; they are in the table below and in the JSON.

Every 4th of 60 samples, from the table stimulus.

The same rig also ran:

Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample

Category static · sample time 0.1 · 60 steps · commit 3c100aff6f27235305db4ad4d572f32e342718ad · produced by docsSample --out <folder> --blocks Decibel_Conversion --steps 60 · data docs/generated/samples/Control_Systems__Spectral_Measurements__Decibel_Conversion.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).