Signal Generator — Control Systems/Sources

Control_Systems/Sources/Signal_Generator · 0 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Description#

The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.

Signal Generator

Control Systems / Sources

A source producing one of four waveforms from the simulation clock, at a chosen amplitude and frequency:

sine – y = A·sin(ω·t)
square – −A over the first half of each cycle, +A over the second
sawtooth – y = A·(1 − 2·frac(φ)), a ramp falling from +A to −A across each cycle
random – a fresh value drawn uniformly from [−A, +A] every sample

where φ = f·t is the phase in cycles and frac(x) = x − floor(x).

Ports

Output – the generated signal, always a scalar. It has no inputs; the waveform comes from the block's own clock, and the random waveform from its own generator and seed.

Parameters

Waveform – which of the four to generate. This selects the implementation rather than retuning one, so each is a separate code path:
- sine – the default; a plain sinusoid through the origin, with no phase or bias term. Use the Sine Wave block where those are wanted.
- square – starts low: −A until the half-cycle, then +A. It is not the sign of the sine, which would start high.
- sawtooth – falls. Each cycle begins at +A and ramps down to −A, then jumps back.
- random – uniform on [−A, +A], redrawn every sample.
Amplitude – the peak A. A single value; this block does not take vector parameters.
Frequency – the rate, read in the units chosen below. Must be a single value.
Frequency Units – how Frequency is read:
- rad/sec – the default; the value is ω directly, so a full cycle takes 2π/ω seconds.
- Hertz – the value is cycles per second, so ω = 2πf.
The setting changes what the number means, not merely its scale.
Seed – the starting state of the generator behind the random waveform, and ignored by the other three. The same seed always produces the same sequence, so a run is reproducible and two blocks with different seeds are independent. Any whole number.
Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It also sets how finely the waveform is resolved, so a coarse rate visibly aliases a fast one and turns the sawtooth's ramp into a staircase.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Each uses a per-block local sample clock rather than a global one. The chosen Waveform and Frequency Units are structural and are baked into the exported body – the generated core carries the one waveform, not a run-time switch – while Amplitude and the rate are exposed as tunable parameters. The random waveform produces the identical sequence in all ten, because the generator is a 32-bit linear congruential generator using only integer arithmetic and so needs no agreement between platform maths libraries; its seed is baked in, being structural.

The three HDL targets are simulation-only: they read the testbench's simulation time and carry the phase in real arithmetic, quantizing only on the way out to the fixed-point signal ports. On those three the rate is inlined as an exact real literal rather than passed as a Q16.16 parameter port, and deliberately so – a rate quantized to the 1.5×10⁻⁵ Q-format step would accumulate a phase error that grows with the length of the run, which on the sawtooth's jump is a whole-amplitude disagreement rather than a small one. Amplitude remains a tunable port.

Simulink bridge

Import and export, mapped to simulink/Sources/Signal Generator. "Waveform" to WaveForm and "Frequency Units" to Units, both 1:1 over the same names Simulink uses and therefore lossless in either direction; "Amplitude" to Amplitude and "Frequency" to Frequency.

Two caveats. "Sampling Time (s)" does not cross – Simulink's Signal Generator defines no SampleTime parameter at all, so the block runs at the surrounding Simulink rate and an explicit rate here stays on the ICore side. And "Seed" has no counterpart: Simulink's block offers no seed for its random waveform, so the three deterministic waveforms cross exactly while random crosses as a waveform rather than as a sequence – statistically the same, sample for sample different.

Notes

Time-driven. The sine, square and sawtooth waveforms are stateless: the output depends only on the current time. The random waveform is stateful – it carries its generator state, which is reset at the start of every run, so a re-run reproduces the sequence exactly, as does a freshly exported core.
The square and sawtooth waveforms are discontinuous. A continuous solver does not step onto their jumps, so the transition lands on whichever sample follows it; at a coarse rate that is visible as jitter in the edge position.
Scalar only. Simulink's block can take vector parameters and produce a vector; this one takes a single value for each and reports a run error naming the block if given anything else. Use several blocks, or a Mux, for a vector of independent waveforms.

Code facts#

Fact	Value
registered type	`Control_Systems/Sources/Signal_Generator`
family	`Control_Systems/Sources`
solver environment class	`ICoreBlock_0_Control_Systems_1_Sources_2_Signal_Generator`
source	`src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sources/Signal_Generator/ICoreBlock_0_Control_Systems_1_Sources_2_Signal_Generator.cpp`
header	`src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sources/Signal_Generator/ICoreBlock_0_Control_Systems_1_Sources_2_Signal_Generator.h`
default size on canvas	70 × 70 px
ports at insert	0 in, 1 out
code generators implemented	`Python`, `MATLAB`, `Java`, `Rust`, `C`, `C++`, `VHDL`, `Verilog`, `SystemVerilog`, `PLC Structured Text`

Ports#

#	Direction	Signal type	Description label
1	out	`ICoreDouble`	—

Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.

Configuration variables#

Config variable	Default	Simulink parameter
`Waveform`	`sine%~%square%~%sawtooth%~%random~~sine`	`WaveForm`
`Amplitude`	`1`	`Amplitude`
`Frequency`	`1`	`Frequency`
`Frequency Units`	`rad/sec%~%Hertz~~rad/sec`	`Units`
`Seed`	`0`	not crossed

Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.

Simulink bridge#


support	`Support::Both`
Simulink path	`simulink/Sources/Signal Generator`
port-count rule	`PortsParam::None`
`SampleTime` parameter	no — the counterpart defines none; the rate stays on the ICore side
deliberately not crossed	`Seed`

ICore config	Simulink parameter	Value translation
`Waveform`	`WaveForm`	`sine` → `sine`, `square` → `square`, `sawtooth` → `sawtooth`, `random` → `random`
`Amplitude`	`Amplitude`	passes through
`Frequency`	`Frequency`	passes through
`Frequency Units`	`Units`	`rad/sec` → `rad/sec`, `Hertz` → `Hertz`

Caveat (shown to the user): the random waveform crosses as a WAVEFORM but not as a SEQUENCE - Simulink draws from its own generator and exposes no seed, so an exchanged model is statistically identical and sample-wise different. The sine, square and sawtooth waveforms cross exactly. "Sampling Time (s)" does not cross either: the Simulink block defines no SampleTime parameter, so it runs at the surrounding Simulink rate

Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h

Description vs code#

The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.

The verdict above is tools/docs/check_block_descriptions.py (P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.

The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).

Signal Generator block — one of four waveforms from the simulation clock sine y = A*sin(w*t) square y = -A on the first half of each cycle, +A on the second sawtooth y = A*(1 - 2*frac(phi)) a FALLING ramp, +A down to -A random y = A*(2*u - 1), u a fresh uniform on 0,1) every sample

where phi = f_cyc * t (the phase in CYCLES) and frac(x) = x - floor(x).

THE THREE CONVENTIONS THAT ARE NOT GUESSABLE. Every one of these was read off simulink/Sources/Signal Generator in R2026a rather than assumed, and each would have produced a block that fails parity in a way that reads as a codegen bug:

SQUARE STARTS LOW. It is -A on [0, 0.5) of each cycle and +A on [0.5, 1), so it is

NOT A*sign(sin(w*t)) -- that would start high, and would also have to decide what sign(0) means at t=0 and at every half period.

SAWTOOTH FALLS. It leaves +A at the start of each cycle and ramps DOWN to -A, the

opposite direction to MATLAB's own sawtooth() function.

UNITS CHANGE THE MEANING OF Frequency, not just its scale: rad/sec makes the

parameter w directly, Hertz makes it f_cyc directly.

Checked against the real block over 4.5 s at Ts = 0.005, for both unit settings and at non-integer frequencies (0.7 Hz and 3.3 rad/s): every sample agreed EXACTLY, residual 0.

WHY w AND f_cyc ARE BOTH CARRIED. Whichever the user typed is exact, and the other costs one multiply or divide by 2*pi. Deriving the used one FROM the other would round twice -- a sine at Units=rad/sec would reach w as 2*pi*(f/(2*pi)) -- and parity runs at 1e-9, so that is not academic. omegaRad() and freqCycles() each go straight to the config.

WHY THE RANDOM WAVEFORM HAS A SEED AND SIMULINK'S DOES NOT. Code-export verification compares ten generated cores against this C++ one SAMPLE by sample, so the random waveform has to produce the identical stream in ten languages. That needs a seed, and it rules out every language's own RNG -- hence the same hand-written 32-bit LCG that Band-Limited White Noise uses, for the same reason. Simulink's block offers no seed, so the config is listed in the catalog entry's ignoredParams and the random waveform is the one that does not cross sample-for-sample. See the description.

Code export: all ten targets. The three HDL ones are SIMULATION-ONLY -- they read the testbench's sim_time and carry the phase in real arithmetic, quantizing only on the way out to the Q16.16 signal port.

Sample results#

Plotted: free — No input: the block run alone

Category source · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data [docs/generated/samples/Control_Systems__Sources__Signal_Generator.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).

Signal Generator — Control Systems/Sources

Description#