Repeating Sequence Stair — Control Systems/Sources
Control_Systems/Sources/Repeating_Sequence_Stair · 0 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Repeating Sequence Stair
Control Systems / Sources
A source that steps through a list of values, one per sample, and starts again at the end:
y[k] = values[k mod N], where N is how many values there are
There is no time axis and no interpolation – the output is a staircase whose steps are exactly one sample wide, so the waveform's period is N times the block's sampling time.
Ports
- Output – the current entry of the table, always a scalar. It has no inputs; the position in the sequence comes from the block's own index, advancing once per sample.
Parameters
- Output Values – the sequence, as a row or column vector; both spell the same list. Any values are allowed, repeats included, and the LENGTH is what sets the cycle: five values make a five-sample cycle. Must hold at least one value; a single value makes the block a constant.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. On this block it is also the width of each step, since one sample is one entry – so it, together with the number of values, is what sets the period of the waveform.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The table is baked into the arithmetic at export time rather than exposed as a tunable parameter, and it has to be: its length IS the cycle, so the values and the wrap cannot be separated into a tunable part and a fixed one. It is emitted as a chain of comparisons on the index rather than an array, which is the one shape all ten targets spell the same way. Alone among the repeating sources this block reads no clock at all – it counts its own invocations – so the three HDL targets are not simulation-only here; they are an ordinary indexed register.
The HDL caveat is range rather than timing. A signal is carried in Q16.16 there, which reaches 32767, so a table entry outside that cannot be represented even though the software targets carry it without trouble.
Simulink bridge
Import and export, mapped to
simulink/Sources/Repeating Sequence Stair. "Output Values" to
OutValues, with the same meaning on both sides. The rate crosses too,
but under Simulink's own name for it: this block is a masked subsystem there and
calls its rate parameter tsamp rather than SampleTime
(verified against the R2026a block dialog) – so "Sampling Time (s)" maps to
tsamp, exactly as Counter Limited and Tapped Delay do for the same
reason.
Notes
- Stateful: the whole state is the index into the table, which starts at 0 at the beginning of every run, so a re-run reproduces the sequence exactly.
- Discrete by nature, so it always takes its period from its own "Sampling Time (s)".
- The sequence is driven by SAMPLES, not by elapsed time. Changing the rate changes how quickly the staircase advances but not the values it visits.
- See Repeating Sequence Interpolated for the same idea with a time axis and a choice of lookup rules, and Repeating Sequence for a linearly interpolated one.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Sources/Repeating_Sequence_Stair |
| family | Control_Systems/Sources |
| solver environment class | ICoreBlock_0_Control_Systems_1_Sources_2_Repeating_Sequence_Stair |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sources/Repeating_Sequence_Stair/ICoreBlock_0_Control_Systems_1_Sources_2_Repeating_Sequence_Stair.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sources/Repeating_Sequence_Stair/ICoreBlock_0_Control_Systems_1_Sources_2_Repeating_Sequence_Stair.h |
| default size on canvas | 80 × 70 px |
| ports at insert | 0 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Output Values | [3 1 4 2 1] | OutValues |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Sources/Repeating Sequence Stair |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| rate parameter name | tsamp |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Output Values | OutValues | passes through |
Caveat (shown to the user): the rate crosses as 'tsamp' - Simulink's Repeating Sequence Stair is a masked subsystem and does not use the standard 'SampleTime' parameter name
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Repeating Sequence Stair block — one table entry per sample, cycling forever y[k] = values[k mod N] N = how many values there are
The simplest of the three repeating sources: no time axis and no interpolation, just a list stepped through one entry per SAMPLE and started again at the end. The cycle length is the length of the list, so the waveform's period is N * (this block's sampling time).
Verified against simulink/Sources/Repeating Sequence Stair: with [0.7 -1.3 2.1 0.4] and tsamp equal to the model step, that block emits 0.7, -1.3, 2.1, 0.4, 0.7, ... beginning at t = 0, which is what this one does. Driven at a tsamp three times the model step it holds each entry for three model samples, which is the same behaviour seen from a faster clock.
Discrete by nature (setDiscreteOnlyBlock): the index advances once per SAMPLE, so the block must take its period from its own "Sampling Time (s)" rather than be pushed through a continuous solver's intermediate stages, which would advance it several times per step.
WHY THE TABLE IS A BRANCH CHAIN AND NOT AN ARRAY, in all ten targets. An array literal is spelled ten different ways -- and in the three HDL targets it is a constrained type declaration rather than a literal at all -- whereas a chain of comparisons on the index is the same shape everywhere and needs no declaration. The table is structural in any case: its LENGTH is the cycle, so the values and the wrap cannot be separated into a tunable part and a fixed part. The same choice, for the same reason, that Polynomial makes with its coefficients.
Code export: all ten targets, none of them simulation-only -- the block reads no clock, so the HDL cores are an ordinary indexed register. The one HDL caveat is RANGE, not timing: a signal is Q16.16 there, so table entries outside +/-32767 do not fit. See the description.
Sample results#
Plotted: free — No input: the block run alone
Category source · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Sources__Repeating_Sequence_Stair.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).