Random Number — Control Systems/Sources
Control_Systems/Sources/Random_Number · 0 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Random Number
Control Systems / Sources
A source producing a fresh normally distributed number every sample:
y[k] = mean + √variance · g[k], where g[k] is a standard normal draw
Unlike Band-Limited White Noise, nothing is held: each sample is an independent draw, so the variance below is the variance of the output itself rather than a power spectral density that a hold turns into one.
Ports
- Output – the random signal, always a scalar. It has no inputs; the sequence comes from the block's own generator and seed.
Parameters
- Mean – the centre of the distribution, a single value. It is added to every draw, so a nonzero mean shifts the whole signal without changing its spread.
- Variance – the spread, as a variance and not a standard deviation: the output's standard deviation is its square root, so a variance of 4 gives a signal that mostly falls within ±4 (two sigma). Must be zero or more; zero makes the block a constant at the mean.
- Seed – the generator's starting state. The same seed always produces the same sequence, so a run is reproducible and two blocks with different seeds are independent. Any whole number.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. On this block it is also how often a new number is drawn, since there is exactly one draw per sample.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text, and every one of them produces the identical sequence – the generator is a 32-bit linear congruential generator feeding a sum of twelve uniforms, which uses only integer arithmetic and addition and so needs no agreement between platform maths libraries. The mean and the standard deviation are exposed as tunable parameters; the seed is baked in at export time, being structural. The three HDL targets are simulation-only: they carry the generator in real arithmetic, because the 32-bit generator state does not fit in the Q16.16 datapath at all.
Simulink bridge
Neither direction. Simulink has a counterpart –
simulink/Sources/Random Number, whose Mean,
Variance and Seed line up one for one with the three
parameters above – but its sequence comes from Simulink's own random
number generator and cannot be reproduced by generated code. An exported model
would therefore be statistically identical and sample-wise different, which no
parity test could confirm and no user could rely on. Rather than assert a mapping
that nothing verifies, the bridge reports this block and skips it. To cross a model
containing one, place the Simulink block by hand and copy the three values across:
the meanings match exactly, and only the stream will differ. The same situation,
and the same choice, as Band-Limited White Noise.
Notes
- Stateful: the generator state is the whole of it, and it is reset at the start of every run, so a re-run reproduces the sequence exactly, as does a freshly exported core.
- Discrete by nature, so it always takes its period from its own "Sampling Time (s)".
- The draw is a sum of twelve uniforms rather than a Box-Muller transform. That is an exact standard normal in mean and variance, and indistinguishable from one for control work, but it has no tails beyond ±6 standard deviations – worth knowing if the model under test is specifically about rare large excursions.
- Two blocks in one model with the same Seed produce the same sequence and are therefore perfectly correlated. Give them different seeds.
- See Band-Limited White Noise for the same generator held across a noise period, which is what a continuous-time model usually wants.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Sources/Random_Number |
| family | Control_Systems/Sources |
| solver environment class | ICoreBlock_0_Control_Systems_1_Sources_2_Random_Number |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sources/Random_Number/ICoreBlock_0_Control_Systems_1_Sources_2_Random_Number.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sources/Random_Number/ICoreBlock_0_Control_Systems_1_Sources_2_Random_Number.h |
| default size on canvas | 80 × 70 px |
| ports at insert | 0 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Mean | 0 | — |
Variance | 1 | — |
Seed | 0 | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): Simulink's Random Number matches this block parameter for parameter (Mean, Variance, Seed) but not SAMPLE for sample: its sequence comes from Simulink's own random number generator, which generated code cannot reproduce. An exchanged model would be statistically identical and numerically different, and no parity test could confirm it - so the mapping is reported here rather than asserted. Place the Simulink block by hand and copy the three values across if you need it
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Random Number block — a fresh normal draw every sample y[k] = mean + sqrt(variance) * g[k] g[k] a fresh standard-normal draw
The plain normal source: one draw per sample, no holding. Band-Limited White Noise is the same generator with a hold across a noise period and a power-spectral-density parameter in front of it; this block is the discrete-time one, where the variance IS the variance of the output rather than something derived from a rate.
WHY THE GENERATOR IS WRITTEN BY HAND, and why it is the SAME one Band-Limited White Noise uses. Code-export verification compares each of the ten generated cores against this C++ one SAMPLE BY SAMPLE, so a noise source has to produce the identical stream in ten languages or fail its whole row. That rules out every language's own RNG, and it also rules out Box-Muller, whose log and cos agree only to within each platform's libm. What is left is a 32-bit LCG feeding an Irwin-Hall sum -- integer arithmetic and addition, nothing else -- which is bit-identical everywhere including the five backends that have no unsigned integer type at all. See the header for why the intermediates stay exact in a double.
WHY THERE IS NO SIMULINK BRIDGE, for the same reason Band-Limited White Noise has none. The parameters correspond one for one (Mean, Variance, Seed), but the STREAM cannot: Simulink's numbers come from its own generator, so an exported model would be statistically identical and sample-wise different, and no parity testbench could ever pass. Registering the block as exportable would assert a mapping that nothing checks, so it registers Support::None with that reason and the bridge reports it rather than emitting something that quietly disagrees.
Code export: all ten targets. The three HDL ones are SIMULATION-ONLY -- they carry the generator in real arithmetic, because a Q16.16 datapath cannot hold the 32-bit LCG state at all, let alone advance it.
Sample results#
Plotted: free — No input: the block run alone
Category source · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Sources__Random_Number.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).