Constant — Control Systems/Sources
Control_Systems/Sources/Constant · 0 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Constant
Control Systems / Sources
A source that emits one fixed value for the whole run:
y = K
Ports
- Output – the constant K. It has no inputs, and its size is the size of the Constant Value parameter: a scalar value gives a scalar signal, an [m,n] value gives an [m,n] signal.
Parameters
- Constant Value – K itself. A scalar (
2.75), a vector ([1 2 3]) or a matrix ([1 2; 3 4]); whatever shape is entered becomes the output's shape, so this is the parameter that decides the port size rather than one that has to agree with anything. - Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. The value emitted never changes, so the rate only decides how often the port is refreshed.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. K is exposed as a tunable parameter on the generated core rather than being inlined, so a deployed core can be re-pointed at a different constant without regenerating it. Alone among the sources this block needs no local clock on any target – it does not read time – and the three HDL targets are genuinely synthesizable rather than simulation-only: K is a Q16.16 literal driven onto the signal, with no real arithmetic anywhere.
Simulink bridge
Import and export, mapped to simulink/Sources/Constant.
"Constant Value" to Value, "Sampling Time (s)" to
SampleTime, as on every block. Simulink's remaining parameters are
left at their defaults: OutDataTypeStr, OutMin,
OutMax and LockScale are its fixed-point tooling, which
ICore has no counterpart for because every ICore signal is a double, and
VectorParams1D distinguishes a 1-D vector from an Nx1 matrix, a
distinction ICore does not draw. Note the defaults differ on the two sides:
Simulink's SampleTime defaults to inf (a constant sample
time, evaluated once), while ICore's default of 0 inherits the surrounding rate.
The exported value is whatever this block carries, so a rate set here crosses
faithfully – but a model round-tripped through Simulink will come back with
an explicit rate rather than inf.
Notes
- Algebraic and stateless, and the only source in the family that is also time-INDEPENDENT: the output is the same at every instant, so nothing about it changes if the solver's rate or start time does.
- The shape rule is the block's one subtlety. A Constant wired into a port that expects a different size is a size disagreement reported by the receiving block, not by this one – this block has no size to reconcile, it simply announces the one its parameter has.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Sources/Constant |
| family | Control_Systems/Sources |
| solver environment class | ICoreBlock_0_Control_Systems_1_Sources_2_Constant |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sources/Constant/ICoreBlock_0_Control_Systems_1_Sources_2_Constant.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sources/Constant/ICoreBlock_0_Control_Systems_1_Sources_2_Constant.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 0 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Constant Value | 1 | Value |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Sources/Constant |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Constant Value | Value | passes through |
Caveat (shown to the user): Simulink's SampleTime defaults to 'inf' (constant sample time) where ICore's default of 0 inherits the surrounding rate, so a round trip returns an explicit rate rather than 'inf'. Its fixed-point parameters (OutDataTypeStr, OutMin, OutMax, LockScale) and VectorParams1D have no ICore counterpart and are left at their defaults.
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Constant block — y = K, a signal that never changes The simplest source in the library: it emits its "Constant Value" parameter and nothing else. It is neither time-driven nor stateful, so unlike Step, Sine Wave and Chirp Signal it needs no local clock on any target — the whole block is one assignment per element.
The parameter's SHAPE is the output's shape. A scalar gives a scalar port, "[1 2; 3 4]" gives a 2x2 port, which is how a Constant feeds a matrix-valued input (a State Space's initial condition, a Gain's matrix operand).
Code export: all ten targets, and the three HDL ones are genuinely synthesizable here rather than simulation-only — a constant is a Q16.16 literal driven onto the signal, with no clock, no real arithmetic and nothing to quantize at run time.
Sample results#
Plotted: free — No input: the block run alone
Category source · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Sources__Constant.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).