Constant — Control Systems/Sources
Control_Systems/Sources/Constant · 0 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Constant
Control Systems / Sources
A source that emits one fixed value for the whole run:
y = K
Ports
- Output – the constant K. It has no inputs, and its size is the size of the Constant Value parameter: a scalar value gives a scalar signal, an [m,n] value gives an [m,n] signal.
Parameters
- Constant Value – K itself. A scalar (
2.75), a vector ([1 2 3]) or a matrix ([1 2; 3 4]); whatever shape is entered becomes the output's shape, so this is the parameter that decides the port size rather than one that has to agree with anything. - Output data type – the type the output port carries. The list is every numeric type the application knows, so it grows when the application does. Defaults to a 64-bit float, which changes nothing.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. The value emitted never changes, so the rate only decides how often the port is refreshed.
Choosing a type
The value you type is not converted here – the output port applies the type when the value is stored, exactly once, which is what makes a simulation and the code generated from it agree on the answer. An integer type truncates toward zero and then wraps to its width, so a Constant Value of 3.7 on an 8-bit signed output is 3, and 200 is −56. A boolean output stores 1 for any non-zero value and 0 otherwise. Set the type here when the constant IS an integer or a flag; put a Data Type Conversion block after it when a computed signal has to change type further down.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. K is exposed as a tunable parameter on the generated core rather than being inlined, so a deployed core can be re-pointed at a different constant without regenerating it. Alone among the sources this block needs no local clock on any target – it does not read time – and the three HDL targets are genuinely synthesizable rather than simulation-only: K is a Q16.16 literal driven onto the signal, with no real arithmetic anywhere.
That last sentence holds for the default 64-bit float output. Choosing any other Output data type makes VHDL, Verilog and SystemVerilog not applicable for the diagram: those three carry every signal in one fixed-point format and do not yet apply a signal's type to it, so the export is refused by name with the reason rather than producing a number that would differ from the simulation. The other seven targets carry every type this block offers.
Simulink bridge
Import and export, mapped to simulink/Sources/Constant.
"Constant Value" to Value, "Output data type" to
OutDataTypeStr, and "Sampling Time (s)" to SampleTime,
as on every block. The output type is written only when it is not the default, so
a model of ordinary 64-bit-float Constants exports exactly the script it always
did. Simulink's remaining parameters are
left at their defaults: OutMin,
OutMax and LockScale are its fixed-point tooling, which
ICore has no counterpart for, and
VectorParams1D distinguishes a 1-D vector from an Nx1 matrix, a
distinction ICore does not draw. Note the defaults differ on the two sides:
Simulink's SampleTime defaults to inf (a constant sample
time, evaluated once), while ICore's default of 0 inherits the surrounding rate.
The exported value is whatever this block carries, so a rate set here crosses
faithfully – but a model round-tripped through Simulink will come back with
an explicit rate rather than inf.
Notes
- Algebraic and stateless, and the only source in the family that is also time-INDEPENDENT: the output is the same at every instant, so nothing about it changes if the solver's rate or start time does.
- A 64-bit integer output is exact only to about 9 007 199 254 740 992 (253): values are carried as 64-bit floats during a run, and a 64-bit float cannot hold every 64-bit integer.
- Text is not offered here. A text constant is a different block – String Constant – because its value is typed as text rather than as a number, and this block's value field cannot express one.
- The shape rule is the block's one subtlety. A Constant wired into a port that expects a different size is a size disagreement reported by the receiving block, not by this one – this block has no size to reconcile, it simply announces the one its parameter has.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Sources/Constant |
| family | Control_Systems/Sources |
| solver environment class | ICoreBlock_0_Control_Systems_1_Sources_2_Constant |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Sources/Constant/ICoreBlock_0_Control_Systems_1_Sources_2_Constant.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Sources/Constant/ICoreBlock_0_Control_Systems_1_Sources_2_Constant.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 0 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Constant Value | 1 | Value |
Output data type | outputTypeComboSpec() | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Sources/Constant |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Constant Value | Value | passes through |
Caveat (shown to the user): Simulink's SampleTime defaults to 'inf' (constant sample time) where ICore's default of 0 inherits the surrounding rate, so a round trip returns an explicit rate rather than 'inf'. OutDataTypeStr now DOES cross, through outputTypeParam below, and is written only when the output type is not the default -- so an all-double Constant produces exactly the script it produced before. OutMin, OutMax, LockScale and VectorParams1D still have no ICore counterpart and are left at their defaults.
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Constant block — y = K, a signal that never changes The simplest source in the library: it emits its "Constant Value" parameter and nothing else. It is neither time-driven nor stateful, so unlike Step, Sine Wave and Chirp Signal it needs no local clock on any target — the whole block is one assignment per element.
The parameter's SHAPE is the output's shape. A scalar gives a scalar port, "[1 2; 3 4]" gives a 2x2 port, which is how a Constant feeds a matrix-valued input (a State Space's initial condition, a Gain's matrix operand).
Code export: all ten targets, and the three HDL ones are genuinely synthesizable here rather than simulation-only — a constant is a Q16.16 literal driven onto the signal, with no clock, no real arithmetic and nothing to quantize at run time.
⚠ IT IS ALSO THE SECOND BLOCK IN THE LIBRARY WHOSE OUTPUT TYPE IS A PARAMETER. "Output data type" re-types the output port on every configuration load, so a Constant can source an integer or a boolean signal rather than only a 64-bit float. THE VALUE IS NOT CONVERTED HERE: this block returns the parameter matrix unchanged and the PORT applies the type when it stores it -- 3.7 into an 8-bit signed output becomes 3, and 200 becomes -56, by the application's one write-time rule (truncate toward zero, then wrap to the width) and not by anything in this file.
Two consequences worth stating where they will be met. Choosing any type but the default makes the three hardware-description targets not applicable for a diagram holding that block, because their fixed-point carrier does not yet apply a signal's type -- the block keeps its synthesizable output for the 64-bit-float case, which is the default. And the type is what crosses to Simulink as
OutDataTypeStr, written only when it is not the default, so an ordinary Constant produces exactly the script it produced before this existed.
Sample results#
Plotted: free — No input: the block run alone
Category source · sample time 0.01 · 60 steps · commit 89f81d5a3 · produced by docsSample --out <folder> --blocks Logical_Operator,Bitwise_Operator,Relational_Operator,Switch,Data_Type_Conversion,Constant --steps 60 · data docs/generated/samples/Control_Systems__Sources__Constant.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).