XY Graph — Control Systems/Sinks
Control_Systems/Sinks/XY_Graph · 2 input / 0 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
XY Graph
Control Systems / Sinks
Plots one signal against another instead of against time: the first input is the abscissa, the second the ordinate, and every step contributes one point (x[k], y[k]) to the chart attached to the block. A phase portrait, a hysteresis loop or a force-displacement curve is exactly this picture, and none of them is legible on a Scope, where the two signals would be drawn as separate traces over t.
Ports
- x – the abscissa, of any size [m,n].
- y – the ordinate. It must carry the same number of elements as x, in any shape; a mismatch is reported and stops the run rather than plotting a pairing the block had to invent.
- No outputs – the XY Graph is a pure sink.
Curves
One curve per element pair, in row-major order over both inputs: element k of x against element k of y. Two scalars draw one curve; a [3,1] against a [3,1] draws three.
Parameters
- Sampling Time (s) – how often a point is taken. Zero or less inherits the solver's rate; a positive value samples the curve at that period. On an XY plot the rate sets how finely the curve is drawn, not how far along it gets.
There are deliberately no axis-limit parameters. The chart auto-ranges and can be zoomed and panned interactively, which is strictly more than a fixed window offers – and the R2026a Simulink counterpart has no such parameter left to map to either.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text – but a deployable target has no display, so what each emits is not a plot. The nine console targets print one <x>,<y> pair per curve per step, which is the data behind the picture and plots directly in anything that reads two columns. PLC Structured Text emits comments only, naming the exact signal array entries to tap, since ST has no console; attach an HMI or trace there instead.
Simulink bridge
Import and export, mapped to simulink/Sinks/XY Graph. There are no
parameters to carry, and the two input ports are fixed on both sides, so nothing
has to describe the port count. In R2026a that library path adds Simulink's
newer Record block preset to two ports rather than the old XY Graph mask,
which is why the mask's xmin/xmax/ymin/
ymax/st parameters are not mapped: they no longer
exist. The Record block has no SampleTime parameter either, so
"Sampling Time (s)" does not cross.
Notes
- The curves live inside the chart and are cleared at the start of every run. To keep the data for later analysis, feed the same two signals to a Signal Recorder or a To File.
- Unlike the Scope, the horizontal axis is not time, so a rolling time window would mean nothing here – the whole curve stays on the chart for the whole run.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Sinks/XY_Graph |
| family | Control_Systems/Sinks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Sinks_2_XY_Graph |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sinks/XY_Graph/ICoreBlock_0_Control_Systems_1_Sinks_2_XY_Graph.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sinks/XY_Graph/ICoreBlock_0_Control_Systems_1_Sinks_2_XY_Graph.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 2 in, 0 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | x |
| 2 | in | ICoreDouble | y |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Sinks/XY Graph |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
Caveat (shown to the user): in R2026a this library path adds Simulink's Record block preset to two ports; it has no SampleTime parameter, so "Sampling Time (s)" does not cross
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0Ports lists 3 entries for 2 ports (2 in, 0 out) — grouped, or one undocumented? a reader must say
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
XY Graph block -- plots the second input against the first, instead of against time One point (x[k], y[k]) per step, per element pair. A phase portrait, a hysteresis loop or a force-displacement curve is exactly this picture, and none of them is legible on a Scope.
Code export: a deployable target has no display, so the nine console targets print the "<x>,<y>" pairs -- the data behind the picture -- and PLC ST names the tap points.
Sample results#
| t | in ICoreDouble-Out-0 | in ICoreDouble-Out-0 | out ICoreDouble-In-0 | out ICoreDouble-In-1 |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0.4 | 0 | 0 | 0 | 0 |
| 0.8 | 0 | 0 | 0 | 0 |
| 1.2 | 1 | 1 | 1 | 1 |
| 1.6 | 1 | 1 | 1 | 1 |
| 2 | 1 | 1 | 1 | 1 |
| 2.4 | 1 | 1 | 1 | 1 |
| 2.8 | 1 | 1 | 1 | 1 |
| 3.2 | 1 | 1 | 1 | 1 |
| 3.6 | 1 | 1 | 1 | 1 |
| 4 | 1 | 1 | 1 | 1 |
| 4.4 | 1 | 1 | 1 | 1 |
| 4.8 | 1 | 1 | 1 | 1 |
| 5.2 | 1 | 1 | 1 | 1 |
Every 4th of 60 samples, from the step stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.8 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 0.9996 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -2 … 3 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category sink · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Sinks__XY_Graph.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).