Stop Simulation — Control Systems/Sinks
Control_Systems/Sinks/Stop_Simulation · 1 input / 0 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Stop Simulation
Control Systems / Sinks
Ends the run the moment its input is nonzero. Any nonzero entry fires it, so a vector or matrix signal stops the run as soon as one of its elements leaves zero; an all-zero signal does nothing. Drive it from a comparison and the model stops itself when the condition it is watching comes true, instead of running out the clock.
Ports
- Input – the stop condition, of any size [m,n]. Read as a logical test only: ≠ 0 stops the run, = 0 does not, and the magnitude of a nonzero value carries no further meaning.
- No outputs – the block is a pure sink.
Parameters
- Sampling Time (s) – how often the condition is tested. Zero or less inherits the solver's rate; a positive value tests it at that period, which also means the run can overshoot the true crossing by up to one period.
Code export
All ten targets: Python, MATLAB, Java, Rust,
C, C++, VHDL, Verilog, SystemVerilog and
PLC Structured Text – but none of them halts. A deployed core
has no simulation to end, and the generated harnesses write their recording
after the sample loop, so a core that returned early would leave no output
at all rather than a shorter one. Every target instead does what a generated
Simulink core does with this block: it latches a stop request and reports
it once, naming the time it fired, then keeps running and lets the surrounding
application decide. The nine console targets print that one line; PLC
Structured Text has no console, so it latches the request and the trip time
onto the function block's own VAR, where an HMI or trace can read
them.
Simulink bridge
Import and export, mapped to simulink/Sinks/Stop Simulation. There are
no parameters to carry on either side. Simulink's block has no
SampleTime parameter, so "Sampling Time (s)" does not cross;
an exported block tests its condition at the surrounding Simulink rate.
Notes
- Stateful only in the sense that the stop is a one-shot: once it has fired, it does not fire again for the rest of the run.
- Stopping runs every block's end-of-run work – a Scope flushes its traces, a Signal Recorder hands its series to the variables space, a To File closes its file – so a stopped run is a finished run, not an abandoned one.
- The block does not stop the synchronous run that code-export verification uses as its reference, because there is no live solver there to stop. That is deliberate, and it is what lets the block be verified: the reference and the exported cores both play the whole time grid out.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Sinks/Stop_Simulation |
| family | Control_Systems/Sinks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Sinks_2_Stop_Simulation |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sinks/Stop_Simulation/ICoreBlock_0_Control_Systems_1_Sinks_2_Stop_Simulation.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sinks/Stop_Simulation/ICoreBlock_0_Control_Systems_1_Sinks_2_Stop_Simulation.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 0 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Sinks/Stop Simulation |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
Caveat (shown to the user): the condition is tested at the surrounding Simulink rate; "Sampling Time (s)" does not cross
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0Ports lists 2 entries for 1 port (1 in, 0 out) — grouped, or one undocumented? a reader must say
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Stop Simulation block -- ends the run when its input goes nonzero Any nonzero entry of the input stops the solver, exactly as Simulink's Stop Simulation block does; an all-zero signal does nothing. One-shot: once fired, it does not fire again for the rest of the run.
Code export: the exported cores LATCH A STOP REQUEST and report it once, rather than ending their sample loop -- see the header for why that is the only behaviour that can be both correct for a deployed core and verifiable.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-In-0 |
|---|---|---|
| 0 | 0 | 0 |
| 0.4 | 0 | 0 |
| 0.8 | 0 | 0 |
| 1.2 | 1 | 1 |
| 1.6 | 1 | 1 |
| 2 | 1 | 1 |
| 2.4 | 1 | 1 |
| 2.8 | 1 | 1 |
| 3.2 | 1 | 1 |
| 3.6 | 1 | 1 |
| 4 | 1 | 1 |
| 4.4 | 1 | 1 |
| 4.8 | 1 | 1 |
| 5.2 | 1 | 1 |
Every 4th of 60 samples, from the step stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.8 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 0.9996 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -2 … 3 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category sink · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Sinks__Stop_Simulation.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).