Signal Recorder — Control Systems/Sinks
Control_Systems/Sinks/Signal_Recorder · 1 input / 0 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Signal Recorder
Control Systems / Sinks
Saves what it receives as a time series in the variables space, so a run's data outlives the run. Recorded series are ordinary variables: visible, editable and readable by the math tool windows (FFT analysis, transfer function estimation, spline fitting).
Ports
- Inputs – one by default, and the count is user-editable. Any signal size is accepted.
- No outputs – the recorder is a pure sink.
Channels
One variable per scalar channel, in port and element order. A single channel takes the configured name exactly as typed; several take name_0, name_1, and so on.
Parameters
- Variable Name – the name to record under. This names something the block creates, so it is not looked up in the variables space; an existing variable of that name is overwritten at the end of the run.
- Max Samples – memory cap. Once reached, the most recent samples are kept and the oldest are dropped.
- Decimation – keep every Nth sample. 1 records every sample.
- Sampling Time (s) – how often a sample is taken. Zero or less inherits the solver's rate.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text – but no target has a variables space, so each records the way that target can be read back. The nine console targets stream one channel,time,value line per retained sample, so the run's transcript is a CSV of exactly the samples the in-app block would have kept, with identical channel names, channel order and decimation. PLC Structured Text instead owns one ring buffer per channel, sized to "Max Samples" – making ST the one target that reproduces the most-recent-N truncation exactly, and leaving the recording observable from an HMI or trace.
Simulink bridge
Import and export, mapped to simulink/Sinks/To Workspace.
"Variable Name" to VariableName, "Max Samples" to
MaxDataPoints, "Decimation" to Decimation,
"Sampling Time (s)" to SampleTime. SaveFormat is
always written as Timeseries: the recorder only ever produces time and
value series, so there is no other shape to offer.
Notes
- The recording is handed over when the run finishes, not while it runs.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Sinks/Signal_Recorder |
| family | Control_Systems/Sinks |
| solver environment class | ICoreBlock_0_Control_Systems_1_Sinks_2_Signal_Recorder |
| source | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sinks/Signal_Recorder/ICoreBlock_0_Control_Systems_1_Sinks_2_Signal_Recorder.cpp |
| header | src/ICoreSDK/ICoreBlockLibrary/Blocks/Control_Systems/Sinks/Signal_Recorder/ICoreBlock_0_Control_Systems_1_Sinks_2_Signal_Recorder.h |
| default size on canvas | 80 × 70 px |
| ports at insert | 1 in, 0 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Variable Name | recorded_signal | — |
Max Samples | std::to_string(FALLBACK_MAX_SAMPLES) | — |
Decimation | 1 | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Sinks/To Workspace |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
CONFIG_VARIABLE_NAME.c_str() | VariableName | passes through |
CONFIG_MAX_SAMPLES.c_str() | MaxDataPoints | passes through |
CONFIG_DECIMATION.c_str() | Decimation | passes through |
Catalog contract: src/ICoreSDK/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0Ports lists 2 entries for 1 port (1 in, 0 out) — grouped, or one undocumented? a reader must sayB03 Simulink params rule(s) this tool cannot resolve
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-In-0 |
|---|---|---|
| 0 | 0 | 0 |
| 0.4 | 0 | 0 |
| 0.8 | 0 | 0 |
| 1.2 | 1 | 1 |
| 1.6 | 1 | 1 |
| 2 | 1 | 1 |
| 2.4 | 1 | 1 |
| 2.8 | 1 | 1 |
| 3.2 | 1 | 1 |
| 3.6 | 1 | 1 |
| 4 | 1 | 1 |
| 4.4 | 1 | 1 |
| 4.8 | 1 | 1 |
| 5.2 | 1 | 1 |
Every 4th of 60 samples, from the step stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 5.8 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | -1 … 0.9996 |
table | Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample | -2 … 3 |
Plotted: step — Step: 0 -> 1 at t = 1 s
Category sink · sample time 0.1 · 60 steps · commit ccf005c8 · produced by docsSample --out <folder> --steps 60 · data docs/generated/samples/Control_Systems__Sinks__Signal_Recorder.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).