Floating Scope — Control Systems/Sinks

Floating Scope

Control Systems / Sinks

Plots signals it is told the names of, against simulation time, on the chart attached to the block – without being wired to any of them. It has no ports at all: drop it anywhere and it watches whatever Signals lists. One trace per scalar channel, so a [3,1] signal draws three lines.

Ports

• None. Not one input, not one output. That is what makes it floating, and it is the whole difference from Scope.

Naming the signals to watch

ICore links carry names, and that name is the selection: rename a link (its name is editable like a block's) and list that name here. A name containing / is matched against the link's full path instead, which is how two links called err in different subsystems are told apart. Matching runs over this block's own subsystem and everything below it, never above – that is exactly the set of signals a generated core contains, so a Floating Scope cannot plot something in the app that its exported code has no name for.

Parameters

• Signals – comma-separated link names, in plot order: err, y_meas, Plant/u_cmd. Empty watches nothing and plots nothing. This names links in the diagram, not variables, so it is never looked up in the variables space. A name that matches no link is reported by name when the run starts, and the remaining names still plot.
• Sampling Time (s) – how often a point is taken. Zero or less inherits the solver's rate; a positive value samples the traces at that period.

Notes

• The traces are one sample behind. Solver order follows input dependencies, and a block with no inputs has none – so this block runs at the head of every step and reads what its sources published on the previous one. Every trace is shifted by one sampling period. That is inherent to watching a signal instead of receiving it: use Scope where the exact sample matters.
• The traces live inside the chart and are cleared at the start of every run. To keep a run's data, use Signal Recorder or Record.
• On an infinite simulation the chart streams and keeps a rolling window rather than the whole history.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The watched signals are ordinary signals in the generated core, so each target reads them by name and prints them per step; a deployable target has no display, exactly as with the Scope. PLC Structured Text emits comments only, naming the exact signal array entries to tap, since ST has no console. The one-sample shift above applies to the exported code too, and for the same reason – so the export agrees with the app.

Code-export verification

This block is excluded from the code-export verification matrix, by name, in ICoreParityRigLibrary::unriggableTypes(). The verifier records a terminal block's input signals and compares them; a block with no inputs records nothing, so a rig around it would fail all ten languages at residual 0 with "Each matrix must have at least two columns" – a red row that says nothing about the block. The exclusion is reported by exportVerify with that reason rather than dropping it silently.

Simulink bridge

Import and export, mapped to simulink/Sinks/Floating Scope. The signal selection does not cross in either direction, and cannot: Simulink stores a floating scope's selection in the scope's own configuration object rather than in a block parameter, so there is no parameter for "Signals" to map to. The block crosses; the list has to be re-picked on the far side, and an imported Floating Scope arrives watching nothing. "Sampling Time (s)" is written to SampleTime as on every block, though Simulink's floating scope normalises it back to inherited (-1).