Variant Start — Control Systems/Signal Routing

Variant Start

Control Systems / Signal Routing

Opens a variant region: it sends its input down one of its branches, the one whose variant control is true, and a Variant End with the same Variant Start End Tag closes the region by passing on that same branch. The branches between them are ordinary blocks. Every block on a branch not chosen leaves the run – a block tapped off that branch included – as Simulink removes it. The choice is made before the run from the project's variables.

Ports

• Input – u, any size [m,n].
• y1 … y_N – one branch per variant control, each of the input's size. Add or remove outputs from the block's port settings, keep one control per output, and give the paired Variant End as many inputs. The chosen branch carries u.

Parameters

• Variant Controls – one control per branch, in port order, written as Simulink writes them, {'V==1';'V==2'}, or as a plain list, V==1; V==2. A control is a condition that is true or false: V==1, V~=1, V>=1 && V<=2, V==1 || W==2, mod(V,2)==1, or true and false. (default) marks the branch taken when no other control is true. A bare name such as V is not a condition and is refused, as Simulink refuses it. The default is {'true';'false'}: the first branch.
• Variant Control Mode – expression evaluates the controls as conditions; label treats each control as a name and takes the branch whose name is Label Mode Active Choice; sim codegen switching takes the branch whose control is (sim), and each control must be (sim) or (codegen).
• Label Mode Active Choice – in label mode, the name of the chosen branch. Unused in the other modes.
• Variant Start End Tag – the name that pairs this block with its Variant End, which must be at the same level. Default A, as in Simulink.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It does not cross to Simulink, whose block has no rate parameter.

When a run is refused

In Simulink's words: no Variant End of the same tag at this level (has no paired Variant End block present in the current hierarchy), no control true (must have at least one active port), more than one true, two (default) controls, a bare name, a variable the project does not define, a value that is not true or false, and a number of controls that is not the number of outputs. ICore also refuses two Variant Ends of the same tag at one level.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The choice is made before the export, so the generated body copies the input to the chosen branch and holds no condition; the branches not chosen are not exported. Re-export after changing a variable a control reads. The HDL targets are fully synthesizable.

Simulink bridge

Import and export, mapped to simulink/Signal Routing/Variant Start. Variant Controls crosses as the cell VariantControls, which is what sets Simulink's output count and its paired End's input count; Variant Control Mode, Label Mode Active Choice and Variant Start End Tag as VariantControlMode, LabelModeActiveChoice and VariantStartEndTag. The activation time is written as update diagram, the only one ICore makes; a model with another is reported on import. The rate does not cross.

Notes

• Algebraic, with no state.
• Simulink also refuses a branch that has no direct path from the Start to the End; ICore does not check that, and runs whatever the branches hold.
• Controls name variables of the project's variables space; Simulink's Simulink.Variant objects and model workspace are not carried.