Variant Sink — Control Systems/Signal Routing

Variant Sink

Control Systems / Signal Routing

Sends its input to one of its outputs, the one whose variant control is true: y_k = u. Each output has a control, a condition over the project's variables such as V==1, and the choice is made before the run from the variables' values then. The outputs that are not chosen are absent: every block they alone feed leaves the run, as Simulink removes it.

Ports

• Input – u, any size [m,n].
• y1 … y_N – the choices, one per variant control, each of the input's size. Add or remove outputs from the block's port settings, and keep one control per output. The chosen one carries u; a block that reads an output not chosen and also something else keeps running and reads 0 from it, as in Simulink.

Parameters

• Variant Controls – one control per output, in port order, written as Simulink writes them, {'V==1';'V==2'}, or as a plain list, V==1; V==2. A control is a condition that is true or false: V==1, V~=1, V>=1 && V<=2, V==1 || W==2, mod(V,2)==1, or true and false. (default) marks the output taken when no other control is true. A bare name such as V is not a condition and is refused, as Simulink refuses it. The default is {'true';'false'}: the first output.
• Variant Control Mode – expression evaluates the controls as conditions; label treats each control as a name and takes the output whose name is Label Mode Active Choice; sim codegen switching takes the output whose control is (sim), and each control must be (sim) or (codegen).
• Label Mode Active Choice – in label mode, the name of the chosen output. Unused in the other modes.
• Allow Zero Variant Controls – Off: a run with no control true is refused. On: with no control true every output is absent, and the block leaves the run with everything after it.
• Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period. It does not cross to Simulink, whose block has no rate parameter.

When a run is refused

In Simulink's words: no control true (must have at least one active port), more than one true (must have only one active port), two (default) controls, a bare name, a variable the project does not define, a value that is not true or false, and a number of controls that is not the number of outputs.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The choice is made before the export, so the generated body copies the input to the chosen output and holds no condition; what the other outputs alone fed is not exported, and an output not chosen that still reaches the exported core's interface carries zeros. Re-export after changing a variable a control reads. The HDL targets are fully synthesizable.

Simulink bridge

Import and export, mapped to simulink/Signal Routing/Variant Sink. Variant Controls crosses as the cell VariantControls, which is what sets Simulink's output count; Variant Control Mode, Label Mode Active Choice and Allow Zero Variant Controls as VariantControlMode, LabelModeActiveChoice and AllowZeroVariantControls. The activation time is written as update diagram, the only one ICore makes; a model with another is reported on import. The rate does not cross.

Notes

• Algebraic, with no state.
• Controls name variables of the project's variables space; Simulink's Simulink.Variant objects and model workspace are not carried.
• To choose by a setting rather than a condition, use Signal Routing / Manual Variant Sink.