State Reader — Control Systems/Signal Routing

State Reader

Control Systems / Signal Routing

Outputs the state of another block, named by its path, with no wire between the two: a Unit Delay’s held sample, a Delay’s line, an integrator’s accumulator, a state-space block’s x. What it reads is the state the owner’s next step starts from.

Ports

• Output x – the owner’s state, in the owner’s shape: a Unit Delay, Integrator or Discrete-Time Integrator gives one element per signal element; a Delay of length N gives one row of N per signal element (a [1x3] for a length-3 Delay on a scalar); a Discrete or continuous State-Space gives its x as an [n x 1] column.

Parameters

• State owner block – the full path of the block whose state is read, as the navigator shows it (Home/A/UD). It follows the block when that block is renamed or moved. Owners: Unit Delay, Delay, Discrete-Time Integrator, Discrete Transfer Fcn, Discrete State-Space, Integrator and State-Space; any other block is refused with Simulink’s words (Block of type … cannot be a state owner block).
• State name – which of the owner’s states; empty (the default) names its one state, which is every owner’s only one.
• Sampling Time (s) – zero or less runs it whenever the subsystem it sits in runs, which is how Simulink’s State Reader takes its rate.

Where it may sit

As in Simulink, the reader and its owner may not share an order the model does not state: placed beside its owner, in the same subsystem, or in another subsystem with nothing ordering the two, the run is refused before its first step with R2026a’s message. The placement that runs is the owner and the reader in two action subsystems of one If or Switch Case: one of them runs on a step, and the reader sees the state the owner holds between its runs.

Code export

Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text: the output is copied, element by element, from where the owner’s own code keeps its state in the generated core (in Rust and C++ the core’s step does the copy at this block’s place, since a block there reaches only itself). A Discrete Transfer Fcn owner is refused by name: its export keeps input and output histories, not the state this block reads. So is an owner or reader inside a reusable subsystem function.

Simulink bridge

Import and export, mapped to simulink/Signal Routing/State Reader. State owner block ↔ StateOwnerBlock: the path crosses relative to the subsystem exchanged and is written as the full path Simulink requires, set once every block exists (Simulink checks the block is there); an owner outside the exchanged subsystem cannot cross and is reported. State name ↔ StateName. "Sampling Time (s)" does not cross: Simulink’s State Reader has no SampleTime parameter and takes the rate of the subsystem it sits in.

Notes

• Measured on R2026a: with a Unit Delay counter (x ← x + 1) as the owner, a reader that runs after the owner on a step sees x[k+1], and one that runs before it sees x[k].