Generated reference › Selector — Control Systems/Signal Routing
kind: generated#block#control-systems-signal-routing

Selector — Control Systems/Signal Routing

Control_Systems/Signal_Routing/Selector · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Description#

The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.

Selector

Control Systems / Signal Routing

Selects entries out of a vector signal by position: y = u(idx). The list of positions is fixed by the dialog and does not change while the model runs, so the output's length is known before the run starts. The output keeps the input's orientation – a column in gives a column out, a row gives a row.

Ports

  • Input – the signal u to select from. It must be a vector: [m,1] or [1,n]. A [1,1] signal is a vector of one entry; a signal with both dimensions above 1 is reported rather than flattened.
  • Output – y, the selected entries in the order they are listed, in the input's orientation. Its length is the number of positions selected, which is generally NOT the input's length: [m,1] in gives [L,1] out and [1,n] gives [1,L].

Parameters

  • Index Mode – what the FIRST entry of the input is called.
    • One-based – the first entry is 1. The default, as in Simulink.
    • Zero-based – the first entry is 0.
  • Index Option – how the list of positions is given. This selects which list is built rather than retuning one, so each option is a separate code path.
    • Select all – every entry, in order. "Indices" and "Output Size" are not read.
    • Index vector (dialog) – the positions listed in "Indices", in the order given. Repeats are allowed; the default.
    • Starting index (dialog) – a contiguous run of "Output Size" entries beginning at the single position in "Indices".
  • Indices – the positions, counted according to Index Mode. A row or column vector under Index vector (dialog) ([1 3] by default), and a single position under Starting index (dialog). Every position must lie inside the input; one that does not stops the run with a message naming it.
  • Output Size – how many entries the contiguous run takes. Read only under Starting index (dialog); a positive whole number.
  • Input Port Width – how many entries the incoming signal has. It must agree with the signal that actually arrives, and a disagreement stops the run. It is not redundant: Simulink's own dialog carries this field and validates the index list against it, so the value has to cross the bridge for a generated script to run at all.
  • Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The whole index list is resolved at export time, so the generated body is a fixed set of copies with constant subscripts – no index arithmetic and no bounds test at run time, and nothing is exposed as a tunable parameter. Re-export after changing the selection. The three HDL targets are fully synthesizable: a gather with constant indices is wiring, so nothing is evaluated in real.

Simulink bridge

Import and export, mapped to simulink/Signal Routing/Selector. "Index Mode" to IndexMode and "Index Option" to IndexOptions, each one option for one option, so both round trips are lossless; "Input Port Width" to InputPortWidth, "Indices" to Indices and "Output Size" to OutputSizes as plain pass-through values. The width is written before the indices, deliberately: Simulink range-checks the index list against the declared width the moment it is set, and setting them the other way round is a hard error that aborts the whole generated script rather than a warning.

NumberOfDimensions is always written as 1 and RuntimeRangeChecks as off. This block selects along ONE dimension with indices that cannot move, so it has no second dimension to offer and nothing to range-check at run time – and pinning both means a Simulink model that uses a second dimension, or takes its indices from a port, is reported on import rather than quietly mapped onto a selection that would answer differently. "Sampling Time (s)" to SampleTime, as on every block.

Notes

  • Algebraic, with no state: the output depends only on the current input.
  • The output is a different SIZE from the input, which is the whole point of the block, and it is fixed for the run. A downstream block that requires its inputs to agree in size must be given signals that do.
  • Repeats are allowed under Index vector (dialog): [2 2 1] is a legal selection and copies the second entry twice.
  • No state space, deliberately. The gather is linear, but the block's output is a different size from its input, so it is not the SISO shape model reduction merges; carrying one would offer it for merges it cannot serve.
  • To pick one entry with an index that ARRIVES ON A WIRE rather than sitting in the dialog, use Signal Routing / Multiport Switch with a single data input – that is what Simulink calls Index Vector.

Code facts#

FactValue
registered typeControl_Systems/Signal_Routing/Selector
familyControl_Systems/Signal_Routing
solver environment classICoreBlock_0_Control_Systems_1_Signal_Routing_2_Selector
sourcesrc/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Routing/Selector/ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Selector.cpp
headersrc/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Routing/Selector/ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Selector.h
default size on canvas80 × 70 px
ports at insert1 in, 1 out
code generators implementedPython, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Ports#

#DirectionSignal typeDescription label
1inICoreDouble—
2outICoreDouble—

Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.

Configuration variables#

Config variableDefaultSimulink parameter
Index ModeZero-based%~%One-based~~One-basedIndexMode
Index OptionSelect all%~%Index vector (dialog)%~%Starting index (dial…IndexOptions
Input Port Width3InputPortWidth
Indices[1 3]Indices
Output Size1OutputSizes

Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.

supportSupport::Both
Simulink pathsimulink/Signal Routing/Selector
port-count rulePortsParam::None
SampleTime parameteryes
always setNumberOfDimensions = 1, RuntimeRangeChecks = off
ICore configSimulink parameterValue translation
Input Port WidthInputPortWidthpasses through
Index ModeIndexModeOne-based → One-based, Zero-based → Zero-based
Index OptionIndexOptionsSelect all → Select all, Index vector (dialog) → Index vector (dialog), Starting index (dialog) → Starting index (dialog)
IndicesIndicespasses through
Output SizeOutputSizespasses through

Caveat (shown to the user): ONE dimension with DIALOG indices. Simulink's second dimension and its two port-driven index options are not offered, and NumberOfDimensions is pinned to 1 so a model using either is reported rather than mapped. "Input Port Width" is written BEFORE "Indices", because Simulink range-checks the one against the other as it applies it

Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h

Description vs code#

The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:

  • B0 no sample under docs/generated/samples/ — nothing to cross-check (P8.1)

The verdict above is tools/docs/check_block_descriptions.py (P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.

File banner (developer view)#

The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).

Selector block -- a fixed gather out of a vector signal y = u(idx), with idx a list of positions the dialog fixes. Three ways to give the list: every position ("Select all"), an explicit vector of them ("Index vector (dialog)"), or a contiguous run named by its first position and its length ("Starting index (dialog)"). "Index Mode" says whether the first entry of the signal is called 0 or 1.

The list is CONSTANT for the run, so the output's length is settled before the run starts and every backend emits the gather as a fixed set of copies -- no index arithmetic, no bounds test, nothing evaluated at run time. That is also why the three HDL targets are fully synthesizable here: a gather with constant indices is wiring.

THE OUTPUT KEEPS THE INPUT'S ORIENTATION -- column in, column out -- which was measured against R2026a rather than assumed: a [10;20;30] column selected at [3 1] came back as a two-entry COLUMN. Getting this wrong transposes every downstream signal without any arithmetic being wrong anywhere.

SCOPE, and it is stated in the description too: ONE dimension, DIALOG indices. Simulink's Selector also does two dimensions and can take its indices from a second input port; a block using either is reported by the bridge rather than mapped onto a selection that would answer differently. NumberOfDimensions is pinned to 1 in the catalog entry for exactly that reason.

⚠ "Input Port Width" IS A REAL CONFIG AND NOT A REDUNDANT ONE. Simulink's own dialog has the field, and it validates the index list against it AT EDIT TIME -- measured: setting Indices to [2 4 5] with the width left at its default of 3 is a hard error, "This parameter must be in the range 1 through 3", which aborts a generated script. So the value has to cross, and it has to be set BEFORE Indices; the catalog entry lists the parameters in that order. ICore checks it against the signal that actually arrives.

Algebraic and stateless. No state space -- see the header.

Sample results#

No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.