Merge — Control Systems/Signal Routing
Control_Systems/Signal_Routing/Merge · 2 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Merge
Control Systems / Signal Routing
Joins the outputs of conditionally executed subsystems into one signal: on each step the output y is the input that was written on that step, and when no input was written y holds its last value. An input is written on a step exactly when the enabled, triggered or action subsystem it comes from runs. Before any input has been written, y is the Initial output.
Ports
- Inputs u1 … un – two by default, and the count is user-editable. Each must be the output of an enabled, triggered or action subsystem (an If or Switch Case branch), read by nothing else, and all must have the same size [m,n].
- Output y – the same size as the inputs.
Parameters
- Initial output – what y reads until the first input is written:
a scalar, broadcast to every entry, or a matrix the size of y.
[], the default, reads 0. - Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust,
C, C++, VHDL, Verilog, SystemVerilog and
PLC Structured Text. The generated step writes y at the Merge's place in
the order, from the same per-step decision that guards each source subsystem:
if a source's subsystem ran, y takes that input. If two sources run on
one step the generated code keeps the higher input, as Simulink does once its
multiple-writer check is off; the live run stops instead (see Notes).
Simulink bridge
Import and export, mapped to simulink/Signal Routing/Merge.
Initial output ↔ InitialOutput, and the input count
↔ Inputs. AllowUnequalInputPortWidths is always
off: a model that turns it on, and so uses
InputPortOffsets, is reported on import. "Sampling Time
(s)" does not cross: Simulink's Merge has no SampleTime
parameter, so a rate set here stays on the ICore side and is reported.
Notes
- Stateful: it keeps the last value written, and whether any has been.
- Refused before the run, by name, as R2026a refuses them: a source that is not the output of an enabled, triggered or action subsystem (an iterated subsystem is not one); a source subsystem output set to reset while disabled; a source that also feeds another block; and inputs of different sizes.
- Two inputs written on the same step stop the live run with the block's
name, R2026a's default (
InvMergeRunTimeMultipleWriters).
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Signal_Routing/Merge |
| family | Control_Systems/Signal_Routing |
| solver environment class | ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Merge |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Routing/Merge/ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Merge.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Routing/Merge/ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Merge.h |
| default size on canvas | 60 × 60 px |
| ports at insert | 2 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u1 |
| 2 | in | ICoreDouble | u2 |
| 3 | out | ICoreDouble | y |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Initial output | [] | InitialOutput |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Signal Routing/Merge |
| port-count rule | PortsParam::MuxCount |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| always set | AllowUnequalInputPortWidths = off |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Initial output | InitialOutput | passes through |
Caveat (shown to the user): Inputs whose widths differ (AllowUnequalInputPortWidths, InputPortOffsets) are not carried.
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.