Manual Variant Sink — Control Systems/Signal Routing
Control_Systems/Signal_Routing/Manual_Variant_Sink · 1 input / 2 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Manual Variant Sink
Control Systems / Signal Routing
Sends its one input down one of N branches, chosen by a setting rather than by a signal: yk = u for the active branch k; every other output is inactive and what it alone feeds leaves the run. There is no control port – the choice belongs to the model, so it is fixed for the whole run. It is the mirror of Manual Variant Source, which chooses among N inputs.
Ports
- Input u – the signal to route, of any size [m,n].
- Outputs – one per branch, two on a fresh block and editable up to 25. Each is the same size [m,n] as the input. The ACTIVE one carries u; every other is inactive (see Notes), and a block that still reads one reads zeros of that size.
Parameters
- Active Choice – which branch receives the input, counted from 1, as Simulink counts its choices. A value outside 1..N is reported, not wrapped and not clamped: a branch that does not exist is a mistake worth stopping for.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The choice is resolved at export time, so no generated body contains a test: the selected branch is a plain copy and the others are constant zeros. The three HDL targets are fully synthesizable – there is no arithmetic to quantize.
Simulink bridge
Import and export, mapped to simulink/Signal Routing/Manual Variant Sink. Active
Choice → LabelModeActiveChoice, whose values Simulink spells
V_1, V_2, … – a bare number is a hard error there, so the
table translates it. The branch count crosses as NumChoices, taken from the
OUTPUT port list, and Simulink accepts it only in 2–25; a block with more branches
than that is reported rather than truncated in silence.
The rate does NOT cross. That block defines no SampleTime parameter
– verified by set_param against R2026a, which answers "ManualVariantSink
block (mask) does not have a parameter named 'SampleTime'" – so "Sampling Time (s)" stays
on the ICore side.
GeneratePreprocessorConditionals is always written off: ICore's ten
backends resolve the choice at export time and emit one branch, and none of them has a
preprocessor to make conditional. A model that had it on is reported on import rather
than arriving as a variant whose code-generation shape silently changed.
Notes
- Algebraic and stateless. Deliberately carries no state space: the block has several outputs, so it is not SISO and model reduction would refuse it whatever it carried.
- The inactive branches leave the run, as Simulink removes them from its compiled
model – measured: driven with 1..6 through two To Workspace blocks,
V_1produced y1 = [1 2 3 4 5 6] and no y2 variable at all. A block fed only by an inactive branch, and everything after it, does not execute and is not exported. A block that also reads a live branch stays and reads 0 from the inactive one, which is what R2026a gives too (a Sum of the inactive branch and a Constant 5 reads 5). Changed on 2026-09-30: before that the downstream blocks ran on the zeros, so one with a side effect – a recorder, a file write, a stop – fired here and not in Simulink.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Signal_Routing/Manual_Variant_Sink |
| family | Control_Systems/Signal_Routing |
| solver environment class | ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Manual_Variant_Sink |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Routing/Manual_Variant_Sink/ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Manual_Variant_Sink.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Routing/Manual_Variant_Sink/ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Manual_Variant_Sink.h |
| default size on canvas | 80 × 90 px |
| ports at insert | 1 in, 2 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | y1 |
| 3 | out | ICoreDouble | y2 |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Active Choice | 1 | LabelModeActiveChoice |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Signal Routing/Manual Variant Sink |
| port-count rule | PortsParam::VariantNumChoicesOut |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| always set | GeneratePreprocessorConditionals = off |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Active Choice | LabelModeActiveChoice | passes through |
Caveat (shown to the user): the active choice crosses as
LabelModeActiveChoice, whose values Simulink spells V_1, V_2, ... , and the branch count asNumChoices, taken from the OUTPUT list and accepted by Simulink only in 2..25; the block has NO SampleTime parameter, so a rate set here does not cross. The INACTIVE branches are removed on both sides: from Simulink's compiled model (measured) and from ICore's run and export (BF3.4); a block that also reads a live branch reads 0 from an inactive one in both
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0Ports lists 2 entries for 3 ports (1 in, 2 out), and the 2 they cover does not reconcile — grouped, or one undocumented? a reader must sayB0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Manual Variant Sink -- one input, N branches, one of them chosen by a setting y<k> = u and every other output is zero, with k the "Active Choice". The mirror of Manual_Variant_Source. See the header for why the zeros are an ICore convention rather than a translation, and for what Simulink was measured to do instead.
THE INACTIVE BRANCHES LEAVE THE RUN, as Simulink removes them (FEATURES_TO_ADD.md BF3.4, since 2026-09-30): loadBlockConfig() marks every other output inactive, and the build prunes whatever they alone feed (ICoreModelBuild::pruneInactiveVariants). A block that also reads a live branch stays and reads 0 from the inactive one -- the one place the zeros below still reach anything, and the one place R2026a shows a 0 too.
ONE PLACE DECIDES THE BRANCH. loadBlockConfig() resolves
selectedonce, and compute_h and all ten generators read it -- so the live run and every export cannot disagree about which output carries the signal. The choice is a model setting, not a signal, so no generated body contains a test: the selected branch is a copy and the others are constants.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.