Data Store Write — Control Systems/Signal Routing
Control_Systems/Signal_Routing/Data_Store_Write · 1 input / 0 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Data Store Write
Control Systems / Signal Routing
Writes its input into the data store it names: the store = u, from
this step on, for every Data Store Read of it, with no wire between them.
Simulink’s Data Store Write
(BlockType=DataStoreWrite).
Ports
- Input – u, the value written. It must be the size of the store exactly; nothing is expanded or cast into a store, as Simulink casts nothing.
Parameters
- Data store name –
A(default). The store to write: the Data Store Memory of that name at this block’s level or the nearest level above it. Case-sensitive, and never looked up in the variables space. A name no Memory declares on that path – a Memory in a subsystem below this block included – stops the run in Simulink’s words (DSMemoryBlockNotFound). - Sampling Time (s) – zero or less inherits the solver’s rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog,
SystemVerilog and PLC Structured Text copy the input into the store, the
exported core’s named global (ds0, …), element by
element; in the three HDLs it goes through the working copy every signal
takes, so a Read later in the same step sees it. An export that does not hold
the store is refused by name.
Simulink bridge
Both directions, as simulink/Signal Routing/Data Store Write.
Data store name goes to DataStoreName; "Sampling Time
(s)" goes to SampleTime, as on every block. Simulink’s
element selection (DataStoreElements, EnableIndexing)
does not cross: a Write here writes the whole store.
Notes
- A Write runs before the Reads of its store in the same step wherever no data path says otherwise. Two Writes of one store in a step run in their order, and the last one wins; its Memory’s Write after write diagnostic reports that, as a warning by default.
- It writes once per step, never at a continuous solver’s intermediate stages. Its Memory’s Write after read diagnostic is checked on each write.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Signal_Routing/Data_Store_Write |
| family | Control_Systems/Signal_Routing |
| solver environment class | ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Data_Store_Write |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Routing/Data_Store_Write/ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Data_Store_Write.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Routing/Data_Store_Write/ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Data_Store_Write.h |
| default size on canvas | 80 × 60 px |
| ports at insert | 1 in, 0 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Data store name | A | DataStoreName |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Signal Routing/Data Store Write |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Data store name | DataStoreName | passes through |
Caveat (shown to the user): The whole store crosses: Simulink's element selection (DataStoreElements, EnableIndexing) does not.
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.