Bus Selector — Control Systems/Signal Routing
Control_Systems/Signal_Routing/Bus_Selector · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Bus Selector
Control Systems / Signal Routing
Takes one named element back out of a bus and puts it on an ordinary wire. The counterpart of Bus Creator: what that block packed under a name, this one unpacks by that name.
Ports
- Input (
bus) – the bus to select from. Only a bus connects here; anything else is refused when you draw the wire. - Output – the chosen element. Its type and size are the element's, not settings of this block: selecting a boolean element gives a boolean output, and selecting a [3,1] element gives a [3,1] output. The port changes type when the model is built, so its colour and badge follow whatever you selected.
Parameters
- Element name – which element to take, spelled exactly as the Bus Creator names it. A name the bus does not carry is an error when the model is built, and the message lists what the bus does carry.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Notes
- Routing only – the value is passed through unchanged, whatever its type.
- Names are matched exactly, including case and spacing.
- Algebraic, with no state, and no state space.
Code export
Exported to Python, MATLAB, C, C++, Java and
Rust, selecting by the element name – the generated code reads
bus["speed"] in Python and bus.speed in the other five, where the bus
is a declared record with one field per element. It therefore picks the same element this
block is configured to pick even if the Bus Creator upstream is reordered.
Not exported to VHDL, Verilog, SystemVerilog or PLC Structured Text: a bus signal cannot reach those targets at all, so neither can a selection from one. The reason for each is on the Bus Creator block, which is where the bus is made.
Simulink bridge
Import and export, mapped to simulink/Signal Routing/Bus Selector.
"Element name" crosses as Simulink's OutputSignals. "Sampling Time
(s)" does not cross. Simulink's Bus Selector is a virtual block with no
SampleTime parameter at all, so an explicit rate here is reported as
staying on the ICore side, in the export report and as a warning in the generated
script. This block selects one element; a Simulink selector choosing
several imports as one block per element.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Signal_Routing/Bus_Selector |
| family | Control_Systems/Signal_Routing |
| solver environment class | ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Bus_Selector |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Routing/Bus_Selector/ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Bus_Selector.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Routing/Bus_Selector/ICoreBlock_0_Control_Systems_1_Signal_Routing_2_Bus_Selector.h |
| default size on canvas | 40 × 110 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++ |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreBus | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Element name | a | OutputSignals |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Signal Routing/Bus Selector |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Element name | OutputSignals | passes through |
Caveat (shown to the user): this block selects ONE element; a Simulink selector choosing several imports as one block per element
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Bus Selector -- takes one named element back out of a bus The output port's TYPE and SIZE both come from the element, so both are set in the sizing loop rather than from config: the upstream spec is what says what the element is, and it is not resolved until the loop has run. See the header for why that differs from Data_Type_Conversion, which re-types from its own config in loadBlockConfig().
Sample results#
This block carries a ICoreBus signal, whose value is text rather than a number and is not something a plot has an axis for. The samples are in the table below, exactly as the run recorded them.
| t | in ICoreDouble-Out-0 | in ICoreBus-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|---|
| 0 | -2 | {'a': -2, 'b': 0} | -2 |
| 0.04 | 0.5 | {'a': 0.5, 'b': 0} | 0.5 |
| 0.08 | -2 | {'a': -2, 'b': 0} | -2 |
| 0.12 | 0.5 | {'a': 0.5, 'b': 0} | 0.5 |
| 0.16 | -2 | {'a': -2, 'b': 0} | -2 |
| 0.2 | 0.5 | {'a': 0.5, 'b': 0} | 0.5 |
| 0.24 | -2 | {'a': -2, 'b': 0} | -2 |
| 0.28 | 0.5 | {'a': 0.5, 'b': 0} | 0.5 |
| 0.32 | -2 | {'a': -2, 'b': 0} | -2 |
| 0.36 | 0.5 | {'a': 0.5, 'b': 0} | 0.5 |
| 0.4 | -2 | {'a': -2, 'b': 0} | -2 |
| 0.44 | 0.5 | {'a': 0.5, 'b': 0} | 0.5 |
| 0.48 | -2 | {'a': -2, 'b': 0} | -2 |
| 0.52 | 0.5 | {'a': 0.5, 'b': 0} | 0.5 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 0 … 1 |
ramp | Ramp: slope 1 from t = 0 | 0 … 0.59 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 0 … 0.9246 |
step | Step: 0 -> 1 at t = 1 s | 0 … 0 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.01 · 60 steps · commit 31d36c2c3 · produced by docsSample --out <folder> --blocks Bus_Creator,Bus_Selector,Logical_Operator,Relational_Operator,Bitwise_Operator,Switch --steps 60 · data docs/generated/samples/Control_Systems__Signal_Routing__Bus_Selector.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).