Steiglitz McBride — Control Systems/Signal Modeling
Control_Systems/Signal_Modeling/Steiglitz_McBride · 1 input / 2 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Steiglitz-McBride
Control Systems / Signal Modeling
Fits an IIR model b(z)/a(z) to the frame on its input, read as an impulse
response, by the Steiglitz-McBride iteration – MATLAB's
stmcb(h, nb, na, niter). It starts from the denominator of
prony(h, 0, na) and then, niter times, prefilters the frame
and a unit impulse by 1/a(z) and re-solves for both polynomials at once:
u = h filtered by 1/a, v = δ filtered by 1/a, [−u1..na | v0..nb]·c = u (least squares), a = [1; c(1:na)], b = c(na+1:end)
where uk is u delayed by k samples. Each pass fits the output error of the previous model more closely than Prony's equation error does.
Ports
- h – the frame to fit, an [L,1] column with the oldest sample first, as MATLAB takes its vector: the impulse response h(1) … h(L). L is read off the wire and must be at least nb + na + 2 and at most 64. A Tapped Delay with Delay Order Oldest turns a stream into such a frame.
- b – the numerator coefficients, [nb+1, 1], in descending powers of z−1.
- a – the denominator coefficients, [na+1, 1], with a(1) = 1.
Parameters
- Numerator Order – nb, 0 to 8.
- Denominator Order – na, 1 to 8.
- Iterations – niter, 1 to 20; MATLAB's default is 5.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text, all from one program, so every target does the same arithmetic in the same order as the simulation. The orders and the frame length are structural; re-export after changing them.
The three HDL targets run the fit in real arithmetic and
quantize only at the ports: simulation-only, not offered as
synthesizable. A least-squares solve has a division by a pivot and a data-dependent
row exchange, neither of which belongs in a Q16.16 datapath.
Simulink bridge
None (Support::None). stmcb is a Signal
Processing Toolbox function and that toolbox ships no Simulink library, so
there is no path a diagram could name. The bridge reports this block rather than
dropping it silently, and it has no parity testbench; code export
verification covers all ten languages.
Notes
- Verified against R2026a: see the source banner for the frame and the
measured agreement with
stmcb. - Each iteration prefilters by the previous denominator, so a frame whose fitted a(z) is unstable makes the next prefilter grow, exactly as it does in MATLAB; the result is then as unreliable there as here.
- ⚠ The least-squares step is solved through the normal equations by Gaussian elimination with partial pivoting, where MATLAB's backslash uses a QR factorization. Both give the least-squares answer; they differ by rounding, which grows with how ill-conditioned the frame is. The measured gap on the banner is for a well-posed frame.
- A frame that does not determine the model – a constant, or all zeros – makes the elimination divide by zero, and the outputs are NaN for that frame, as MATLAB's backslash would warn and answer Inf or NaN too.
- Algebraic: every output depends on this frame alone. It is a fit, not a filter, so it carries no state space.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Signal_Modeling/Steiglitz_McBride |
| family | Control_Systems/Signal_Modeling |
| solver environment class | ICoreBlock_0_Control_Systems_1_Signal_Modeling_2_Steiglitz_McBride |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Modeling/Steiglitz_McBride/ICoreBlock_0_Control_Systems_1_Signal_Modeling_2_Steiglitz_McBride.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Modeling/Steiglitz_McBride/ICoreBlock_0_Control_Systems_1_Signal_Modeling_2_Steiglitz_McBride.h |
| default size on canvas | 150 × 80 px |
| ports at insert | 1 in, 2 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | h |
| 2 | out | ICoreDouble | b |
| 3 | out | ICoreDouble | a |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Numerator Order | 2 | — |
Denominator Order | 2 | — |
Iterations | 5 | — |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::None |
| Simulink path | — |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
Caveat (shown to the user): stmcb is a Signal Processing Toolbox function, not a Simulink library block -- that toolbox ships no Simulink library at all -- so there is no path a diagram could name; the block is reported rather than dropped when a model crosses
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Steiglitz-McBride -- MATLAB's stmcb, an iteratively refined IIR model from a frame a = the denominator of prony(h, 0, na); then
iterationstimes: u = filter(1, a, h), v = filter(1, a, unit impulse) c = the least-squares solution of [ -u delayed 1..na | v delayed 0..nb ] * c = u a = [1; c(1:na)], b = c(na+1 : na+nb+1)Read out of the installed stmcb.m (R2026a): the Prony seed with numerator order ZERO, the default five iterations, and the convmtx columns truncated to the frame's length are MATLAB's. The least-squares step is the normal equations here (ICorePronySupport.cpp says why), where stmcb uses backslash.
Measured against R2026a on the export-verify rig's own frames h0 + w*u, u = -1 .. 1 in 41 steps, where h0 = filter([0.8 -0.3 0.15], [1 -1.1 0.55 -0.12], impulse) + 0.01*sin(1:16): the EXPORTED Python core agrees with stmcb(h, 2, 3, 4) to 3.7e-12 on every frame.
Support::None: stmcb is a Signal Processing Toolbox function and that toolbox ships no Simulink library.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.