LPC To From RC — Control Systems/Signal Modeling
Control_Systems/Signal_Modeling/LPC_To_From_RC · 1 input / 2 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
LPC to/from RC
Control Systems / Signal Modeling
Converts between the linear prediction coefficients A = [1 a1 … ap] and the reflection coefficients K = [k1 … kp] of the same model, either way, by the Levinson step-up (K → A) and step-down (A → K) recursions, and publishes the model's normalised prediction error power P = ∏(1 − km²). This is MATLAB's rc2poly and poly2rc.
Ports
- u – the input vector, an [N,1] column: K ([p,1], p = N) for RC to LPC, A ([p+1,1], p = N−1, N at least 2) for LPC to RC.
- y – the converted vector: A, [p+1,1] starting at 1, or K, [p,1].
- P – the prediction error power ∏(1 − k²) for a unit-power input, a scalar. It goes negative when some |k| > 1 – the model is then unstable, and nothing here refuses it, as Simulink does not.
Parameters
- Conversion – RC to LPC (the default, as Simulink's) or LPC to RC; which way the recursion runs.
- Non-Unity First Coefficient – what to do when an LPC input's first coefficient a0 is not 1:
- Replace it with 1 (the default, as Simulink's) – a0 is IGNORED and a1…ap are used as they are. Measured: an input of 2·A gave kp = 1.2 where A gives 0.6.
- Normalize – every coefficient is divided by a0 first.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The input length and the conversion are baked into the core at export time.
The three HDL targets are simulation-only: they carry the arithmetic in real and quantize only at the port boundary. The step-down divides by 1 − k², which is not bounded away from zero. The cores simulate correctly and are not offered as synthesizable.
Simulink bridge
Import and export, mapped to dsplp/LPC to//from RC – the DSP System Toolbox block (a doubled // is how Simulink writes a slash INSIDE a block name). "Conversion" to conversion (one to one, every option) and "Non-Unity First Coefficient" to error (its first two options, one to one).
perr = on and stability = off are always emitted: each MOVES that block's port list (measured – perr adds the P output, stability a boolean third one), and on/off is the 1 input / 2 output shape this block has.
"Sampling Time (s)" does not cross. dsplp/LPC to//from RC defines no SampleTime parameter – verified against the R2026a block dialog – and set_param on a parameter a block does not define is a hard error that aborts the whole generated script.
Notes
- Stateless and algebraic: the conversion runs on this sample's vector alone.
- K → A → K round-trips to rounding; A and K here are bit for bit what
rc2polyandpoly2rcgive (measured on k = [0.3 −0.45 0.2 0.6], P = 0.44588544000000002 from the block and from the product alike).
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Signal_Modeling/LPC_To_From_RC |
| family | Control_Systems/Signal_Modeling |
| solver environment class | ICoreBlock_0_Control_Systems_1_Signal_Modeling_2_LPC_To_From_RC |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Modeling/LPC_To_From_RC/ICoreBlock_0_Control_Systems_1_Signal_Modeling_2_LPC_To_From_RC.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Modeling/LPC_To_From_RC/ICoreBlock_0_Control_Systems_1_Signal_Modeling_2_LPC_To_From_RC.h |
| default size on canvas | 120 × 80 px |
| ports at insert | 1 in, 2 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | out | ICoreDouble | y |
| 3 | out | ICoreDouble | P |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Conversion | RC to LPC%~%LPC to RC~~RC to LPC | conversion |
Non-Unity First Coefficient | Replace it with 1%~%Normalize~~Replace it with 1 | error |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | dsplp/LPC to//from RC |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| always set | perr = on, stability = off |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Conversion | conversion | RC to LPC → RC to LPC, LPC to RC → LPC to RC |
Non-Unity First Coefficient | error | Replace it with 1 → Replace it with 1, Normalize → Normalize |
Caveat (shown to the user): dsplp/LPC to//from RC has NO SampleTime parameter (verified against the R2026a block dialog), so "Sampling Time (s)" does not cross. 'perr', 'stability' pinned: the other value of each moves that block's port list. Only 'Replace it with 1' and 'Normalize' of 'error' are offered - an exported core has nobody to warn
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
LPC to/from RC block — dsplp's dsplp/LPC to//from RC, measured on R2026a before it was written Converts between the linear prediction coefficients A = [1 a1 ... ap] and the reflection coefficients K = [k1 ... kp] of the same model, either way, by the Levinson step-up (K -> A) and step-down (A -> K) recursions, and publishes the model's normalised prediction error power P = prod(1 - km^2).
The conversions, their measured facts and the ten emitted bodies live in ICoreLpcConversionSupport (the arithmetic) and ICoreStatementProgram (the ten spellings); this file is the block's ports, parameters and Simulink bridge.
Code export: all ten targets. The three HDL ones are SIMULATION-ONLY
realarithmetic.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 [2x1] entry 0 | out ICoreDouble-Out-1 |
|---|---|---|---|
| 0 | -2 | [1, -2] | -3 |
| 0.4 | 0.5 | [1, 0.5] | 0.75 |
| 0.8 | -2 | [1, -2] | -3 |
| 1.2 | 0.5 | [1, 0.5] | 0.75 |
| 1.6 | -2 | [1, -2] | -3 |
| 2 | 0.5 | [1, 0.5] | 0.75 |
| 2.4 | -2 | [1, -2] | -3 |
| 2.8 | 0.5 | [1, 0.5] | 0.75 |
| 3.2 | -2 | [1, -2] | -3 |
| 3.6 | 0.5 | [1, 0.5] | 0.75 |
| 4 | -2 | [1, -2] | -3 |
| 4.4 | 0.5 | [1, 0.5] | 0.75 |
| 4.8 | -2 | [1, -2] | -3 |
| 5.2 | 0.5 | [1, 0.5] | 0.75 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 1 … 1 |
ramp | Ramp: slope 1 from t = 0 | 1 … 1 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 1 … 1 |
step | Step: 0 -> 1 at t = 1 s | 1 … 1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit 4bc64690c · produced by docsSample --out <folder> --blocks LPC_To_From_RC LPC_RC_To_Autocorrelation LPC_To_From_Cepstral LSF_LSP_To_LPC --steps 60 · data docs/generated/samples/Control_Systems__Signal_Modeling__LPC_To_From_RC.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).