LPC To From Cepstral — Control Systems/Signal Modeling
Control_Systems/Signal_Modeling/LPC_To_From_Cepstral · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
LPC to/from Cepstral
Control Systems / Signal Modeling
Converts between an LPC vector A and the cepstral coefficients of the same all-pole model: c0 = ln P = 0 (the model's power is taken as 1), cm = −am − Σk (k/m)·ck·am−k, with am = 0 above the order; the other direction inverts the same recursion.
Ports
- u – A ([p+1,1], N at least 2) for LPCs to cepstral coefficients, or the cepstrum c0…cN−1 ([N,1], N at least 2) for Cepstral coefficients to LPCs.
- y – the cepstrum, [L,1] with L the Cepstrum Length (or p+1 with Length Equals LPC Length on), c0 first; or A, [N,1] – the cepstrum direction always keeps the input's length.
Parameters
- Conversion – LPCs to cepstral coefficients (the default, as Simulink's) or Cepstral coefficients to LPCs.
- Cepstrum Length – L, the number of cepstral coefficients produced, c0 included, a whole number of 1 or more. Defaults to 10. Used only by the LPC-to-cepstrum direction and only while Length Equals LPC Length is off – measured: the reverse direction answered 11 values for 11 inputs at lengths 3, 5 and 10 alike.
- Length Equals LPC Length – off (the default) or on; on, L = p+1.
- Non-Unity First Coefficient – what to do when an LPC input's first coefficient a0 is not 1:
- Replace it with 1 (the default, as Simulink's) – a0 is IGNORED and a1…ap are used as they are. Measured: an input of 2·A gave kp = 1.2 where A gives 0.6.
- Normalize – every coefficient is divided by a0 first.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The input length and the conversion are baked into the core at export time.
The three HDL targets are simulation-only: they carry the arithmetic in real and quantize only at the port boundary. The recursion's terms are not bounded, so a Q16.16 datapath would need a scaling nobody can choose in advance. The cores simulate correctly and are not offered as synthesizable.
Simulink bridge
Import and export, mapped to dsplp/LPC to//from Cepstral Coefficients – the DSP System Toolbox block (a doubled // is how Simulink writes a slash INSIDE a block name, and the library breaks this block's name over two lines). "Conversion" to conversion (one to one, every option), "Cepstrum Length" to nceps, "Length Equals LPC Length" to sizecb and "Non-Unity First Coefficient" to error (its first two options, one to one).
enerpp = assume P equals 1 and outpower = off are always emitted: the other value of each ADDS A PORT (a power input, a power output – measured, the output carried exp(c0)), and this block has one input and one output.
"Sampling Time (s)" does not cross. dsplp/LPC to//from Cepstral Coefficients defines no SampleTime parameter – verified against the R2026a block dialog – and set_param on a parameter a block does not define is a hard error that aborts the whole generated script.
Notes
- Stateless and algebraic.
- c0 is always 0 going this way, because the power is assumed 1; going the other way c0 is read and ignored, since A does not depend on it.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Signal_Modeling/LPC_To_From_Cepstral |
| family | Control_Systems/Signal_Modeling |
| solver environment class | ICoreBlock_0_Control_Systems_1_Signal_Modeling_2_LPC_To_From_Cepstral |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Modeling/LPC_To_From_Cepstral/ICoreBlock_0_Control_Systems_1_Signal_Modeling_2_LPC_To_From_Cepstral.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Modeling/LPC_To_From_Cepstral/ICoreBlock_0_Control_Systems_1_Signal_Modeling_2_LPC_To_From_Cepstral.h |
| default size on canvas | 120 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | out | ICoreDouble | y |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Conversion | LPCs to cepstral coefficients%~%Cepstral coefficients to … | conversion |
Non-Unity First Coefficient | Replace it with 1%~%Normalize~~Replace it with 1 | error |
Cepstrum Length | 10 | nceps |
Length Equals LPC Length | off%~%on~~off | sizecb |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | dsplp/LPC to//from Cepstral\nCoefficients |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| always set | enerpp = assume P equals 1, outpower = off |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Conversion | conversion | LPCs to cepstral coefficients → LPCs to cepstral coefficients, Cepstral coefficients to LPCs → Cepstral coefficients to LPCs |
Cepstrum Length | nceps | passes through |
Length Equals LPC Length | sizecb | on → on, off → off |
Non-Unity First Coefficient | error | Replace it with 1 → Replace it with 1, Normalize → Normalize |
Caveat (shown to the user): dsplp/LPC to//from Cepstral Coefficients has NO SampleTime parameter (verified against the R2026a block dialog), so "Sampling Time (s)" does not cross. 'enerpp', 'outpower' pinned: the other value of each moves that block's port list. Only 'Replace it with 1' and 'Normalize' of 'error' are offered - an exported core has nobody to warn
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
LPC to/from Cepstral block — dsplp's dsplp/LPC to//from Cepstral Coefficients , measured on R2026a before it was written Converts between an LPC vector A and the cepstral coefficients of the same all-pole model: c0 = ln P = 0 (the model's power is taken as 1), cm = -am - sumk (k/m)*ck*am-k, with am = 0 above the order; the other direction inverts the same recursion.
The conversions, their measured facts and the ten emitted bodies live in ICoreLpcConversionSupport (the arithmetic) and ICoreStatementProgram (the ten spellings); this file is the block's ports, parameters and Simulink bridge.
Code export: all ten targets. The three HDL ones are SIMULATION-ONLY
realarithmetic.
Sample results#
Plotted: vector — Sine Wave, [3,1]: amplitudes 1/2/3 at 2 rad/s (tried only because every scalar stimulus was refused)
Category dynamic · sample time 0.1 · 60 steps · commit 4bc64690c · produced by docsSample --out <folder> --blocks LPC_To_From_RC LPC_RC_To_Autocorrelation LPC_To_From_Cepstral LSF_LSP_To_LPC --steps 60 · data docs/generated/samples/Control_Systems__Signal_Modeling__LPC_To_From_Cepstral.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).