Generated reference › LPC RC To Autocorrelation — Control Systems/Signal Modeling
kind: generated#block#control-systems-signal-modeling

LPC RC To Autocorrelation — Control Systems/Signal Modeling

Control_Systems/Signal_Modeling/LPC_RC_To_Autocorrelation · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Description#

The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.

LPC/RC to Autocorrelation

Control Systems / Signal Modeling

Recovers the autocorrelation sequence r[0..p] of the order-p autoregressive process that an LPC vector A, or a reflection-coefficient vector K, describes, normalised so the model's prediction error power is 1: r0 = 1/∏(1 − k²) and r[m] = −Σi a(m)i·r[m−i] through each order's coefficients. This is MATLAB's poly2ac(a, 1) and rc2ac.

Ports

  • u – A ([p+1,1], N at least 2) for LPC to autocorrelation, or K ([p,1]) for RC to autocorrelation.
  • r – the autocorrelation r[0..p], [p+1,1].

Parameters

  • Conversion – LPC to autocorrelation (the default, as Simulink's) or RC to autocorrelation. An LPC input is stepped down to K first.
  • Non-Unity First Coefficient – what to do when an LPC input's first coefficient a0 is not 1:
    • Replace it with 1 (the default, as Simulink's) – a0 is IGNORED and a1…ap are used as they are. Measured: an input of 2·A gave kp = 1.2 where A gives 0.6.
    • Normalize – every coefficient is divided by a0 first.
    Simulink's two other choices (warn, error) are not offered: an exported core has nobody to warn. Ignored for the conversions whose input is not an LPC vector.
  • Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.

Code export

All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The input length and the conversion are baked into the core at export time.

The three HDL targets are simulation-only: they carry the arithmetic in real and quantize only at the port boundary. r0 is a reciprocal of ∏(1 − k²) and the step-down divides by 1 − k². The cores simulate correctly and are not offered as synthesizable.

Simulink bridge

Import and export, mapped to dsplp/LPC//RC to Autocorrelation – the DSP System Toolbox block (a doubled // is how Simulink writes a slash INSIDE a block name). "Conversion" to conversion (one to one, every option) and "Non-Unity First Coefficient" to error (its first two options, one to one).

perr_spec = Assume P = 1 is always emitted: its other value, Via input port, adds a second input, and this block has one.

"Sampling Time (s)" does not cross. dsplp/LPC//RC to Autocorrelation defines no SampleTime parameter – verified against the R2026a block dialog – and set_param on a parameter a block does not define is a hard error that aborts the whole generated script.

Notes

  • Stateless and algebraic.
  • Measured equal to poly2ac(a, 1) and rc2ac(k, 1/∏(1−k²)) to the last bits on k = [0.3 −0.45 0.2 0.6]: r0 = 2.2427285358319837.

Code facts#

FactValue
registered typeControl_Systems/Signal_Modeling/LPC_RC_To_Autocorrelation
familyControl_Systems/Signal_Modeling
solver environment classICoreBlock_0_Control_Systems_1_Signal_Modeling_2_LPC_RC_To_Autocorrelation
sourcesrc/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Modeling/LPC_RC_To_Autocorrelation/ICoreBlock_0_Control_Systems_1_Signal_Modeling_2_LPC_RC_To_Autocorrelation.cpp
headersrc/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Modeling/LPC_RC_To_Autocorrelation/ICoreBlock_0_Control_Systems_1_Signal_Modeling_2_LPC_RC_To_Autocorrelation.h
default size on canvas120 × 70 px
ports at insert1 in, 1 out
code generators implementedPython, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text

Ports#

#DirectionSignal typeDescription label
1inICoreDoubleu
2outICoreDoubler

Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.

Configuration variables#

Config variableDefaultSimulink parameter
ConversionLPC to autocorrelation%~%RC to autocorrelation~~LPC to au…conversion
Non-Unity First CoefficientReplace it with 1%~%Normalize~~Replace it with 1error

Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.

supportSupport::Both
Simulink pathdsplp/LPC//RC to Autocorrelation
port-count rulePortsParam::None
SampleTime parameterno — the counterpart defines none; the rate stays on the ICore side
always setperr_spec = Assume P = 1
ICore configSimulink parameterValue translation
ConversionconversionLPC to autocorrelation → LPC to autocorrelation, RC to autocorrelation → RC to autocorrelation
Non-Unity First CoefficienterrorReplace it with 1 → Replace it with 1, Normalize → Normalize

Caveat (shown to the user): dsplp/LPC//RC to Autocorrelation has NO SampleTime parameter (verified against the R2026a block dialog), so "Sampling Time (s)" does not cross. 'perr_spec' pinned: the other value of each moves that block's port list. Only 'Replace it with 1' and 'Normalize' of 'error' are offered - an exported core has nobody to warn

Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h

Description vs code#

The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.

The verdict above is tools/docs/check_block_descriptions.py (P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.

File banner (developer view)#

The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).

LPC/RC to Autocorrelation block — dsplp's dsplp/LPC//RC to Autocorrelation, measured on R2026a before it was written Recovers the autocorrelation sequence r[0.

The conversions, their measured facts and the ten emitted bodies live in ICoreLpcConversionSupport (the arithmetic) and ICoreStatementProgram (the ten spellings); this file is the block's ports, parameters and Simulink bridge.

Code export: all ten targets. The three HDL ones are SIMULATION-ONLY real arithmetic.

Sample results#

LPC RC To Autocorrelation — Sine Wave, [3,1]: amplitudes 1/2/3 at 2 rad/s (tried only because every scalar stimulus was refused)LPC RC To Autocorrelation — Sine Wave, [3,1]: amplitudes 1/2/3 at 2 rad/s (tried only because every scalar stimulus was refused)050001e4012345t (s)in ICoreDouble-Out-0 [3x1] entry 0out ICoreDouble-Out-0 [3x1] entry 0

Plotted: vector — Sine Wave, [3,1]: amplitudes 1/2/3 at 2 rad/s (tried only because every scalar stimulus was refused)

Category dynamic · sample time 0.1 · 60 steps · commit 4bc64690c · produced by docsSample --out <folder> --blocks LPC_To_From_RC LPC_RC_To_Autocorrelation LPC_To_From_Cepstral LSF_LSP_To_LPC --steps 60 · data docs/generated/samples/Control_Systems__Signal_Modeling__LPC_RC_To_Autocorrelation.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).