Levinson Durbin — Control Systems/Signal Modeling
Control_Systems/Signal_Modeling/Levinson_Durbin · 1 input / 3 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Levinson-Durbin
Control Systems / Signal Modeling
Solves the Yule-Walker system for an autocorrelation sequence, publishing all three things the recursion produces:
- A – the prediction-error filter, p+1 entries with A[0] = 1
- K – the p reflection coefficients
- P – the final prediction error power
The order p is the input port's height minus one. There is no order parameter: the solve is exactly as long as the sequence it is given.
Ports
- r – the autocorrelation sequence, an [p+1,1] column holding lags 0 to p with r[0] first. It should be a genuine autocorrelation (r[0] the largest entry, the sequence positive semi-definite); the recursion is defined for any input but only means something for one of those.
- A – the prediction-error filter, [p+1,1], always starting at 1.
- K – the reflection coefficients, [p,1]. K[m] is also A's last entry at order m, which is the cheapest way to check the two against each other.
- P – the prediction error power, a scalar.
Parameters
- Zero Input Handling – on (the default) or off, and it is a division guard rather than a special case. With it on, an input whose r[0] is zero gives A = [1 0 … 0], K = 0 and P = 0; with it off the same input divides by zero and gives NaN throughout, as its Simulink counterpart does. A non-zero r[0] followed by zeros needs neither: the recursion answers K = 0 at every order and P = r[0] either way.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The order is baked into the core at export time – it is the port's height, which is structural – and the recursion itself is emitted as a loop rather than unrolled.
The three HDL targets are simulation-only: they carry the
arithmetic in real and quantize only at the port boundary. That is
not a shortcut. The recursion divides by an error power that falls by
(1 − K²) at every order, so a Q16.16 divisor is exhausted
well before the last coefficient on any sequence with real structure in it. The
cores simulate correctly and are not offered as synthesizable.
Simulink bridge
Import and export, mapped to dsplp/Levinson-Durbin – the DSP
System Toolbox block, not a core Simulink one. "Zero Input Handling" to
zeroInpHandling.
Two of that block's parameters are always emitted with a fixed value, because
this block offers no choice behind them: coeffOutFcnActive =
A and K and outP = on. Both of them MOVE
that block's port list – measured on R2026a – and only that pair gives
the 1 input / 3 output shape this block has.
"Sampling Time (s)" does not cross. dsplp/Levinson-Durbin defines no
SampleTime parameter at all – verified against the R2026a block
dialog – and set_param on a parameter a block does not define is
a hard error that aborts the whole generated script.
Notes
- Stateless and algebraic: the whole solve runs on this sample's input. There is nothing to seed and nothing carried between steps.
- P here is not P on Autocorrelation LPC. This block reproduces
MATLAB's
levinson; the sibling reproduceslpc, which normalises its autocorrelation by the frame length. On the same data the two agree exactly on A and K and differ by a factor of N on P. Measured on an eight-sample frame at order 4: 9.2530162940466418 here, 1.1566270367558302 there. - K's sign is MATLAB's, and much of the literature writes the reflection coefficient with the other one. Here K[m] equals A's last entry at order m.
- Reach for Autocorrelation LPC instead if what you have is a signal frame rather than an autocorrelation – it computes the sequence and then does exactly this.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Signal_Modeling/Levinson_Durbin |
| family | Control_Systems/Signal_Modeling |
| solver environment class | ICoreBlock_0_Control_Systems_1_Signal_Modeling_2_Levinson_Durbin |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Modeling/Levinson_Durbin/ICoreBlock_0_Control_Systems_1_Signal_Modeling_2_Levinson_Durbin.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Modeling/Levinson_Durbin/ICoreBlock_0_Control_Systems_1_Signal_Modeling_2_Levinson_Durbin.h |
| default size on canvas | 110 × 90 px |
| ports at insert | 1 in, 3 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | r |
| 2 | out | ICoreDouble | A |
| 3 | out | ICoreDouble | K |
| 4 | out | ICoreDouble | P |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Zero Input Handling | on%~%off~~on | zeroInpHandling |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | dsplp/Levinson-Durbin |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| always set | coeffOutFcnActive = A and K, outP = on |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Zero Input Handling | zeroInpHandling | on → on, off → off |
Caveat (shown to the user): dsplp/Levinson-Durbin has NO SampleTime parameter (verified against the R2026a block dialog), so "Sampling Time (s)" does not cross. 'coeffOutFcnActive' and 'outP' are pinned because BOTH move that block's port list - measured, 'A and K' with outP on is the 1 in / 3 out shape this block has, and an ICore port list cannot follow a config
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0every stimulus in the sample errored — cross-checks skipped
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Levinson-Durbin block — solve the Yule-Walker system for an autocorrelation sequence Takes an autocorrelation sequence r = [r0 r1 ... rp] on one port and publishes the three things the recursion produces, on three:
A the prediction-error filter, p+1 entries with A[0] = 1 K the p reflection coefficients P the final prediction error power
The ORDER IS THE PORT HEIGHT MINUS ONE. There is no order parameter: a Levinson solve is exactly as long as the sequence it is given, and taking p from the port is what stops the two disagreeing.
⚠ THREE OUTPUTS RATHER THAN AN OUTPUT-SELECTION MODE, AND THAT IS A MEASUREMENT ABOUT SIMULINK. dsplp/Levinson-Durbin has
coeffOutFcnActive(A and K | A | K) andoutP, and BOTH MOVE ITS PORT LIST — measured, 'A and K' with outP on is 1 in / 3 out. An ICore port list is registered once and cannot follow a config, so both are pinned as fixed parameters and the block always publishes all three. An unconnected output costs nothing, and the same choice is what Window Function and Gaussian RF Pulse made.⚠ THE RECURSION AND ITS CONVENTIONS WERE MEASURED BEFORE ANY OF THIS WAS WRITTEN, against the FUNCTION
levinsonand against the BLOCK, driven side by side. The C++ that ships was then compiled outside the application and diffed a second time: 60 vectors over four signals at orders 1, 2 and 4, worst 8.3e-16 relative. What that settled is in ICoreLinearPredictionSupport.h, beside the code it justifies — the reflection coefficient's sign, the order update having to read the previous A, and the zero-input flag being a division guard and nothing else.⚠ THIS BLOCK'S P IS
levinson's e AND ITS SIBLING'S ISlpc's g, WHICH DIFFER BY THE FRAME LENGTH. Autocorrelation LPC computes its own autocorrelation and normalises it by N, so on the same data the two blocks agree exactly on A and K and differ by a factor of N on P. Measured on an eight-sample frame at order 4: 9.2530162940466418 here against 1.1566270367558302 there.Code export: all ten targets. The three HDL ones are SIMULATION-ONLY
realarithmetic, quantizing at the port boundary only — the recursion divides by an error power that falls by (1 - k^2) at every order, which a Q16.16 divisor does not survive. Recursive IIR's call, for the same reason.
Sample results#
No stimulus produced a sampled output in this rig — Invalid input size at Levinson-Durbin block: ICore Blocks/Home/Levinson Durbin. That is a fact about the single-block rig, not a verdict on the block: an offline batch fit, a block whose output only appears at onSolverFinish, or one that needs a driven environment cannot be exercised alone.
Category unsampled · sample time 0.1 · 60 steps · commit 9208dc677 · produced by docsSample --out <folder> --blocks Levinson_Durbin Autocorrelation_LPC --steps 60
Sample data: docs/generated/samples/Control_Systems__Signal_Modeling__Levinson_Durbin.json