Burg AR Estimator — Control Systems/Signal Modeling
Control_Systems/Signal_Modeling/Burg_AR_Estimator · 1 input / 3 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Burg AR Estimator
Control Systems / Signal Modeling
Fits an order-p autoregressive model to a signal frame by Burg's method: x[n] + a1x[n−1] + … + apx[n−p] = e[n], and publishes the prediction-error filter A = [1 a1 … ap], the p reflection coefficients K and the variance G of the white noise e that drives the model. This is MATLAB's arburg.
Burg's recursion runs a forward and a backward prediction error down the frame, one sample shorter per order, and picks each reflection coefficient to minimise their summed power: km = −2·Σebef / Σ(ef² + eb²). The coefficients follow by the Levinson order update and the error variance starts at x′x/N, shrinking by (1 − km²) per order.
Ports
- u – the signal frame x, an [N,1] column; N must be greater than the order p.
- A – the prediction-error filter, [p+1,1], always starting at 1.
- K – the reflection coefficients, [p,1]; K[m] equals A's last entry at order m.
- G – the error variance, a scalar – the variance itself, not its square root.
Parameters
- Inherit Estimation Order – on or off (default on, as Simulink's). On, the order is p = N−1, the largest the frame allows, and Estimation Order is ignored; off, it is Estimation Order.
- Estimation Order – p, a whole number of 1 or more. Defaults to 4, as Simulink's does.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The frame length and the order are baked into the core at export time.
The three HDL targets are simulation-only: they carry the arithmetic in real and quantize only at the port boundary. The solve divides by a running error power that shrinks at every order, which a Q16.16 datapath does not survive. The cores simulate correctly and are not offered as synthesizable.
Simulink bridge
Import and export, mapped to dspparest3/Burg AR Estimator – the DSP System Toolbox block. "Inherit Estimation Order" to inheritOrder (on/off, one to one) and "Estimation Order" to ord.
fcn = A and K is always emitted: it MOVES that block's port list – measured on R2026a, A and K is the 1 input / 3 output shape this block has.
"Sampling Time (s)" does not cross. dspparest3/Burg AR Estimator defines no SampleTime parameter at all – verified against the R2026a block dialog – and set_param on a parameter a block does not define is a hard error that aborts the whole generated script.
Notes
- Stateless and algebraic: the whole solve runs on this sample's frame. Nothing is carried between steps.
- G is the variance, not the standard deviation. Measured on a 16-sample frame at order 4: the Simulink block answers 0.43240702424919097 and
arburg's e is 0.43240702424919075; its square root would be 0.658. - An all-zero frame gives NaN, as the Simulink block does – measured on the estimator: A = [1 NaN …], K = NaN, G = NaN. There is no guard to switch on; feed it a frame with energy in it.
- Reach for the Burg Method block for the spectrum this model implies.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Signal_Modeling/Burg_AR_Estimator |
| family | Control_Systems/Signal_Modeling |
| solver environment class | ICoreBlock_0_Control_Systems_1_Signal_Modeling_2_Burg_AR_Estimator |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Modeling/Burg_AR_Estimator/ICoreBlock_0_Control_Systems_1_Signal_Modeling_2_Burg_AR_Estimator.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Modeling/Burg_AR_Estimator/ICoreBlock_0_Control_Systems_1_Signal_Modeling_2_Burg_AR_Estimator.h |
| default size on canvas | 120 × 90 px |
| ports at insert | 1 in, 3 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | u |
| 2 | out | ICoreDouble | A |
| 3 | out | ICoreDouble | K |
| 4 | out | ICoreDouble | G |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Inherit Estimation Order | on%~%off~~on | inheritOrder |
Estimation Order | 4 | ord |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | dspparest3/Burg AR Estimator |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| always set | fcn = A and K |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Inherit Estimation Order | inheritOrder | on → on, off → off |
Estimation Order | ord | passes through |
Caveat (shown to the user): dspparest3/Burg AR Estimator has NO SampleTime parameter (verified against the R2026a block dialog), so "Sampling Time (s)" does not cross. 'fcn' is pinned to 'A and K' because it MOVES that block's port list - measured, 'A and K' is the 1 in / 3 out shape this block has
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0every stimulus in the sample errored — cross-checks skipped
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Burg AR Estimator block — an order-p AR model of a signal frame by Burg's method MATLAB's
arburg, and the DSP System Toolbox block dspparest3/Burg AR Estimator, both measured on R2026a before a line of this was written. It publishesA the prediction-error filter, p+1 entries with A[0] = 1 K the p reflection coefficients G the error VARIANCE (not its square root)
⚠ THREE OUTPUTS BECAUSE
fcn= 'A and K' IS PINNED: that parameter MOVES the Simulink block's port list (measured: 'A' gives 1 in / 2 out, 'A and K' 1 in / 3 out), and an ICore port list is registered once and cannot follow a config.'Inherit Estimation Order' maps one to one onto
inheritOrder, whose Simulink default is ON: p = N-1, measured (A came back with N entries on a 12-sample frame).The solve, the spectrum and all ten emitted bodies live in ICoreArEstimationSupport, beside the measurements that justify them; this file is the block's ports, parameters and bridge.
Code export: all ten targets. The three HDL ones are SIMULATION-ONLY
realarithmetic -- the solve divides by quantities a Q16.16 datapath cannot carry.
Sample results#
No stimulus produced a sampled output in this rig — Invalid input size at Burg AR Estimator block: ICore Blocks/Home/Burg AR Estimator. That is a fact about the single-block rig, not a verdict on the block: an offline batch fit, a block whose output only appears at onSolverFinish, or one that needs a driven environment cannot be exercised alone.
Category unsampled · sample time 0.1 · 60 steps · commit 358d2d933 · produced by docsSample --out <folder> --blocks Burg_AR_Estimator Yule_Walker_AR_Estimator Covariance_AR_Estimator Modified_Covariance_AR_Estimator Burg_Method Yule_Walker_Method Covariance_Method Modified_Covariance_Method --steps 60
Sample data: docs/generated/samples/Control_Systems__Signal_Modeling__Burg_AR_Estimator.json