Unit Conversion — Control Systems/Signal Attributes
Control_Systems/Signal_Attributes/Unit_Conversion · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Unit Conversion
Control Systems / Signal Attributes
Converts a signal from one physical unit to another, elementwise: y = a·u + b. The factor a and the offset b are not entered – they follow from the pair of units chosen. Each unit is held as its own affine map onto the SI base unit of its quantity (xSI = scale·x + offset), so the pair collapses to a = scalein/scaleout and b = (offsetin − offsetout)/scaleout. Converting degC to K therefore gives a = 1, b = 273.15; degC to degF gives a = 1.8, b = 32; rad to deg gives a = 180/π, b = 0.
The two units must measure the same quantity. Metres into seconds has no factor, so the block reports both names and stops the run rather than answering a number.
Ports
- Input – the signal u, in the input unit, of any size [m,n].
- Output – y, the same value in the output unit, and always the same size as the input. The block never reshapes a signal.
Parameters
- Input Unit – the unit the incoming signal is already in. Chosen from the list below; defaults to degC. inherit reads it off the wire instead: the unit the signal carries from the subsystem port upstream that sets one, as Simulink's Unit Conversion does.
- Output Unit – the unit to convert to. The same list; defaults to K.
inherit reads it off the wires downstream: the unit set on the subsystem port the output
feeds, directly or through other subsystem ports. With either one at inherit and no unit
reaching it, the run stops and says which side has none – Simulink stops the model
too. A unit read off a wire is spelled as Simulink's unit database spells it (
W*h,cal_th,gn,km/(h*s)), which is the spelling a subsystem port's Unit takes. Both lists offer the same units, grouped here by the quantity they measure – a pair drawn from two different groups is refused:- Temperature – K, degC, degF, degR. The only group with an offset, which is what makes this block affine rather than a gain.
- Angle – rad, deg, rev.
- Angular velocity – rad/s, deg/s, rpm. Kept apart from Frequency deliberately: Hz and rad/s differ by 2π and are not interchangeable.
- Acceleration – m/s^2, ft/s^2, km/s^2, in/s^2, km/h-s, mph/s, G. G is the standard gravity, 9.80665 m/s² exactly – a defined constant rather than a local measurement, which is what makes it a unit.
- Angular acceleration – rad/s^2, deg/s^2, rpm/s. Kept apart from Acceleration for the reason Angular velocity is kept apart from Velocity: a radian is not a metre.
- Length – m, km, cm, mm, in, ft, mi, nmi. nmi is the international nautical mile, 1852 m by definition.
- Velocity – m/s, km/h, km/s, ft/s, ft/min, in/s, mph, kn.
- Mass – kg, g, lbm, slug. A slug is the mass one pound-force accelerates at one ft/s² – 14.5939 kg, and 32.174 lbm.
- Density – kg/m^3, lbm/ft^3, slug/ft^3, lbm/in^3. The first two imperial rows differ by that same 32.174, which is exactly the confusion a from/to pair exists to prevent.
- Force – N, kN, lbf.
- Pressure – Pa, kPa, bar, psi, psf, atm. psf is pounds-force per square FOOT, psi/144, which is how aerodynamic pressures are usually quoted.
- Energy – J, kJ, Wh, kWh, cal, BTU.
- Power – W, kW, hp (the mechanical horsepower, 550 lbf·ft/s).
- Torque – N*m, lbf*ft.
- Time – s, ms, min, h.
- Frequency – Hz, kHz, MHz.
- Current – A, mA.
- Voltage – V, mV, kV.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The pair of units is resolved to the two numbers a and b before anything is emitted, and those two are inlined into the arithmetic rather than exposed as tunable parameters – a generated core carries no unit names and no table, only one multiply and one add. Retuning a deployed core to a different unit pair therefore means exporting again.
The three HDL targets are synthesizable, with the fixed-point range caveat that applies to any arithmetic there: the datapath is Q16.16, so a pair whose factor carries the signal outside ±32768 – kWh into J multiplies by 3.6×106 – will not fit, exactly as a Gain of the same size would not. Choose the pair, or rescale, with the datapath in mind.
Simulink bridge
Imports and exports, in both directions, with both units at inherit, as
simulink/Signal Attributes/Unit Conversion. Measured against R2026a: that block has
exactly one parameter, OutputType, and no unit parameters at all –
it reads the unit off the incoming SIGNAL and the outgoing one from what the signal downstream
declares, both set on Inport and Outport blocks rather than on the converter. That is what this
block does with both units at inherit, so that is the block that crosses: an imported
Unit Conversion arrives with both at inherit, and a Simulink model exported from a subsystem
port in m through it into one in cm computes 300 for 3 in R2026a, as
here. With a unit chosen from the list, the block is reported and not written when a model
containing it is exchanged, and its conversion is left on the ICore side: a block emitted
anyway would sit in the Simulink model converting between whatever units its neighbours
happened to declare, which is a wrong answer rather than a missing one.
That block also defines no SampleTime parameter – set_param
against R2026a answers "UnitConversion block does not have a parameter named 'SampleTime'"
– so "Sampling Time (s)" stays on the ICore side.
Aerospace Blockset is the other half of this answer, and it is a different reason.
Its aerolibconvert2 library ships eleven conversion blocks – one per
quantity, each with an IU / OU pair that is exactly what this block's
two parameters are, and none of them with a SampleTime either. Any one of them
would map cleanly; the trouble is that a catalog entry names one Simulink path for one
ICore type, and this block spans eighteen quantities at once. Splitting it into eleven blocks to
gain the bridge would trade a table a user reads once for eleven blocks they have to choose
between, so those eleven stay unmapped and the coverage stays here. The factors are the same ones:
every unit this block shares with that family was checked against convang,
convangvel, convangacc, convacc, convvel,
convlength, convmass, convdensity,
convforce, convpres and convtemp in R2026a, and they
agree to the last bit.
Notes
- Algebraic and stateless – the output depends only on the current sample.
- Deliberately carries no state space, even for the pairs where the offset works out to zero and the block really is a gain. The constant term has nowhere to live in A/B/C/D, and making the block's linearity depend on which units are selected would mean model reduction absorbed it under one pair and refused it under another. Refusing it always is the clearer contract.
- The two unit choices are picked from a list rather than typed. That is not only about typos: a free-text parameter is looked up in the variables space first, so a unit named K or m would begin resolving to a user variable of that name the moment one existed, and the block would quietly convert something else.
- A pair drawn from two different quantities is a stopped run with both names in the message, not a silent pass-through.
- Adding a unit is adding one row to the table this block's dialog and arithmetic are both generated from, so a unit can never be offered and be unknown to the conversion. The three quantities and six units added for the Aerospace family (acceleration, angular acceleration, density; nmi, slug, psf, km/s, in/s, ft/min) changed no existing factor and no default.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Signal_Attributes/Unit_Conversion |
| family | Control_Systems/Signal_Attributes |
| solver environment class | ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_Unit_Conversion |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Attributes/Unit_Conversion/ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_Unit_Conversion.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Attributes/Unit_Conversion/ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_Unit_Conversion.h |
| default size on canvas | 80 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Input Unit | unitOptions("degC") | not crossed |
Output Unit | unitOptions("K") | not crossed |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Signal Attributes/Unit Conversion |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| deliberately not crossed | Input Unit, Output Unit |
Caveat (shown to the user): crosses only with both units at inherit, which is what Simulink's Unit Conversion is: it takes no unit parameters and reads both units off the signals either side of it (the Inport and Outport Unit). With a unit chosen from the list it is reported and not written; rebuild that conversion on the Simulink side as a Gain (and a Bias, for a temperature)
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The lists agree. check_block_descriptions.py finds no disagreement between the description's Ports, Parameters, Code export and Simulink bridge lists and the code's.
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Unit Conversion -- converts a signal from one physical unit to another y = a*u + b, elementwise, with a and b derived from the two units chosen rather than entered. See the header for the affine-to-SI table the pair collapses through, for why a cross-quantity pair is refused rather than answered, and for why the two choices are option variables rather than free text.
ONE PLACE CONVERTS, TEN BACKENDS INLINE THE RESULT. The pair is resolved once per run into the two doubles a and b, and the live solver and all ten generators read those same two numbers -- so no target can disagree with the simulation about what a unit means, and no generated core carries a unit table.
Sample results#
| t | in ICoreDouble-Out-0 | out ICoreDouble-Out-0 |
|---|---|---|
| 0 | -2 | 271.1 |
| 0.4 | 0.5 | 273.6 |
| 0.8 | -2 | 271.1 |
| 1.2 | 0.5 | 273.6 |
| 1.6 | -2 | 271.1 |
| 2 | 0.5 | 273.6 |
| 2.4 | -2 | 271.1 |
| 2.8 | 0.5 | 273.6 |
| 3.2 | -2 | 271.1 |
| 3.6 | 0.5 | 273.6 |
| 4 | -2 | 271.1 |
| 4.4 | 0.5 | 273.6 |
| 4.8 | -2 | 271.1 |
| 5.2 | 0.5 | 273.6 |
Every 4th of 60 samples, from the table stimulus.
The same rig also ran:
| Stimulus | What it is | Output range |
|---|---|---|
impulse | Impulse: one sample of 1 at k = 5, 0 elsewhere (Repeating Sequence Stair) | 273.1 … 274.1 |
ramp | Ramp: slope 1 from t = 0 | 273.1 … 278.9 |
sine | Sine Wave: amplitude 1, 2 rad/s, no phase, no bias | 272.2 … 274.1 |
step | Step: 0 -> 1 at t = 1 s | 273.1 … 274.1 |
Plotted: table — Repeating Sequence Stair: [-2 -1 -0.5 0 0.5 1 2 3], one entry per sample
Category static · sample time 0.1 · 60 steps · commit 6b92ba358550e2e95cbea403c8651bd04562c427 · produced by docsSample --out <folder> --blocks Unit_Conversion --steps 60 · data docs/generated/samples/Control_Systems__Signal_Attributes__Unit_Conversion.json · the SVG is generated from those numbers by tools/docs/plot_svg.py, so it is a run and not a drawing (R-D10).