Signal Specification — Control Systems/Signal Attributes
Control_Systems/Signal_Attributes/Signal_Specification · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Signal Specification
Control Systems / Signal Attributes
Passes its input through unchanged – y = u – and asserts that the signal arriving has the size it was told to expect. The arithmetic is the identity; the check is the point of the block. It lets a model state at one point on a wire what is supposed to be flowing there, and be stopped with a message naming that block when something else is.
That is worth having because signal sizes here are inferred: the model build resolves every port by a convergence loop over the whole diagram, so a wrong size introduced at one block is usually reported somewhere else entirely.
Ports
- Input – the signal u, of any size [m,n], subject to the check below.
- Output – y, always the SAME size as the input and carrying the same values. The block never reshapes and never rescales a signal.
Parameters
- Dimensions – the shape the input must have. Three forms:
- -1 – inherit: accept whatever arrives. This is the default, and it makes the block a pure pass-through.
- n (a scalar) – accept any signal of exactly n elements, whatever its [m,n] shape. This is the width, the same count the Width block reports.
- [m n] – accept only that exact shape, rows and columns both.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Every one of them emits a straight copy. The declared shape is deliberately not carried into the generated code: it is checked when the model is built, and on a deployed core the signal sizes are fixed at export time, so a re-check could never fail and would only cost each target a branch. The three HDL targets are therefore trivially synthesizable – there is no arithmetic to quantize.
Simulink bridge
Import and export, mapped to simulink/Signal Attributes/Signal Specification.
"Dimensions" maps to Dimensions, with the same three forms and the same
-1 meaning inherit, so the mapping is 1:1 and lossless in both directions.
"Sampling Time (s)" maps to SampleTime, as on every block.
Simulink's block carries further declarations that have no counterpart here and are
left at their Simulink defaults: OutMin and OutMax (a design range,
which Simulink checks only when the model asks it to), OutDataTypeStr and
LockScale (every ICore signal is a matrix of doubles), SignalType
(there are no complex signals here), Unit, VarSizeSig and
BusOutputAsStruct.
Notes
- Algebraic, with no state: the output is the input, sample for sample.
- The check runs once, when the model is built, not on every step – and only on a pass where every port in the diagram already agrees, so what it reports is a settled size rather than a half-resolved one.
- Deliberately carries no state space, even though the identity is perfectly linear. Absorbing this block into a neighbour would discard the assertion the user put there on purpose, so model reduction reports it as unmergeable instead.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Signal_Attributes/Signal_Specification |
| family | Control_Systems/Signal_Attributes |
| solver environment class | ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_Signal_Specification |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Attributes/Signal_Specification/ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_Signal_Specification.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Attributes/Signal_Specification/ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_Signal_Specification.h |
| default size on canvas | 80 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Dimensions | -1 | Dimensions |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Signal Attributes/Signal Specification |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Dimensions | Dimensions | passes through |
Caveat (shown to the user): the further declarations Simulink's block carries have no counterpart here and are left at their defaults: OutMin/OutMax are a design range, OutDataTypeStr and LockScale are types (every ICore signal is a matrix of doubles), and SignalType, Unit, VarSizeSig and BusOutputAsStruct describe attributes this tree's signals do not carry
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Signal Specification -- pass the signal through, and assert the shape it should have y = u. See the header for the three forms "Dimensions" takes and for why the assertion is the point of the block rather than an extra on it.
The check lives in verifyInitializedPortSignals() and NOWHERE ELSE. That is deliberate: initializePortSignalSize() runs repeatedly while the model build converges port sizes, and a size that does not yet agree is normal there rather than wrong -- a block that reported from that pass would flood the run log with complaints about sizes that settle a moment later.
All ten exports are a straight copy. The declared shape is NOT emitted into them: it has already been checked when the model was built, and re-checking it on a deployed core would cost every target a branch to test something that cannot have changed.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.