Signal Conversion — Control Systems/Signal Attributes
Control_Systems/Signal_Attributes/Signal_Conversion · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
Signal Conversion
Control Systems / Signal Attributes
Passes its input through unchanged: y = u, entry for entry, at the input's own size. The value is not what the block is for – the copy is. Simulink's counterpart exists to force a signal into one contiguous piece of storage rather than a reference to where its pieces already live, which matters to generated code and to blocks that need a real array behind a signal. Every ICore wire owns its own storage already, so here the block is a deliberate no-op: it carries that intent across the bridge and gives you a place on the canvas to break a reference.
Ports
- Input – the signal u, of any size [m,n].
- Output – y, the same values at the same size, always.
Parameters
- None. The one choice Simulink's dialog offers that is meaningful here – Signal copy – is what the block always does, so there is nothing to set; see Simulink bridge for the two it offers that are not.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. Every one of them emits the same list of per-entry copies with constant subscripts, resolved at export time, and there is no parameter behind any of it. The three HDL targets are therefore pure wiring: no arithmetic, so nothing to quantize and nothing that can differ from the other seven by a fixed-point quantum.
Simulink bridge
Import and export, mapped to simulink/Signal Attributes/Signal Conversion with
ConversionOutput pinned to Signal copy. Simulink's other two
values, Virtual bus and Nonvirtual bus, convert between a bus and a
signal, and ICore has no bus – a wire here carries one matrix of doubles and nothing
structured – so a model using either is reported on import rather than mapped
onto a copy that would carry something else. Simulink's OutDataTypeStr and
OverrideOpt have no counterpart here, every ICore signal being a matrix of
doubles, so they are left at their Simulink defaults.
The rate does NOT cross. That block defines no SampleTime parameter
– verified by set_param against R2026a, which answers "SignalConversion
block does not have a parameter named 'SampleTime'" – so "Sampling Time (s)" stays on
the ICore side. Writing it anyway would be a hard error that aborts the whole generated script
rather than a warning that degrades.
Notes
- Algebraic, with no state: the output is the input, sample for sample.
- Deliberately carries no state space, even though the identity is perfectly linear, for two reasons pointing the same way. The block is a barrier by intent, and a model reduction that absorbed it into a neighbour would discard exactly what a user placed it for; and it accepts any size including matrices, while a feed-through state space needs a D sized from the signal and is defined for the one-in-one-out shape reduction merges. So it is reported as unmergeable rather than folded away.
- To assert a size rather than merely pass one through, use Signal Specification next door, which is the same identity with a dimension check behind it.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Signal_Attributes/Signal_Conversion |
| family | Control_Systems/Signal_Attributes |
| solver environment class | ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_Signal_Conversion |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Attributes/Signal_Conversion/ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_Signal_Conversion.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Attributes/Signal_Conversion/ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_Signal_Conversion.h |
| default size on canvas | 80 × 60 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
No config variable beyond the Sampling Time (s) every block carries.
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Signal Attributes/Signal Conversion |
| port-count rule | PortsParam::None |
SampleTime parameter | no — the counterpart defines none; the rate stays on the ICore side |
| always set | ConversionOutput = Signal copy |
Caveat (shown to the user): ConversionOutput is PINNED to "Signal copy", the one of Simulink's three values that converts between two signals. "Virtual bus" and "Nonvirtual bus" convert between a BUS and a signal, and ICore has no bus -- a wire carries one matrix of doubles -- so a model using either is reported rather than mapped. Simulink's OutDataTypeStr and OverrideOpt have no counterpart here and are left at their defaults. The rate does not cross: the Simulink block defines no SampleTime parameter, so "Sampling Time (s)" stays on the ICore side
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
Signal Conversion -- y = u, and the copy is the point The output is the input, entry for entry, at the input's own size. What the block is FOR is the copy itself: Simulink's counterpart exists to force a signal into one contiguous piece of storage rather than a reference to where its pieces already live. ICore's wires each own their matrix already, so on this side the block is a no-op that carries the intent across the bridge and gives a user a place to break a reference on the canvas.
SCOPE, and it is why this block is small. Simulink's ConversionOutput offers three things: "Signal copy", "Virtual bus" and "Nonvirtual bus". Only the first is a conversion between two SIGNALS; the other two convert between a BUS and a signal, and ICore has no bus -- a wire carries one matrix of doubles and nothing structured. So the catalog entry PINS ConversionOutput to "Signal copy", which is what makes a model using either bus form reported on import rather than mapped onto a copy that would carry something else.
TEN BACKENDS EMIT THE SAME LIST OF COPIES, one per entry with constant subscripts, so the three HDL targets are wiring and there is no arithmetic anywhere to quantize.
Algebraic and stateless. No state space -- see the header.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.