IC — Control Systems/Signal Attributes
Control_Systems/Signal_Attributes/IC · 1 input / 1 output port(s) at insert · exports to Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text
Description#
The block's own DESCRIPTION_HTML, rendered verbatim — the same text the config dialog's info panel and the library navigator show. Fix a wrong sentence in the block's .cpp (R-D9), never here.
IC
Control Systems / Signal Attributes
Forces the signal's value on the first sample only, and is a plain wire after that:
y[0] = Initial Value · y[k] = u[k] for k > 0
The value is applied to every entry of the signal, so one scalar seeds a matrix. Exactly one sample is replaced – this is not a hold, not a bias and not a saturation.
Ports
- Input – the signal u, of any size [m,n]. Its value on the first sample is discarded.
- Output – y, the same size as the input. The block never reshapes a signal.
Parameters
- Initial Value – a scalar, the value every entry of the output takes on the first sample. Defaults to 1, as in Simulink.
- Sampling Time (s) – zero or less inherits the solver's rate; a positive value runs the block at that period.
Code export
All ten targets: Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog and PLC Structured Text. The initial value is baked into the generated code as a constant rather than exposed as a tunable parameter, since it only affects the first sample of a run.
The three HDL targets are synthesizable. The block's whole state is a single
registered flag saying whether the first sample has gone by, so no target needs the
simulation-only sim_time port that the time-driven sources (Step, Ramp) read to
find their place in the run.
Simulink bridge
Import and export, mapped to simulink/Signal Attributes/IC.
"Initial Value" to Value, as a plain pass-through, so the round trip is
lossless. "Sampling Time (s)" maps to SampleTime, as on every block.
Notes
- Stateful, but the state is one FLAG per block rather than a value per entry: all the block remembers is whether the first sample has passed.
- Discrete only. The flag is what makes the block cheap and synthesizable, and it only means "the first sample" if the block is evaluated once per sample – under a continuous solver the Runge-Kutta sub-steps of the very first step would clear it early. The block therefore takes its period from its own Sampling Time (s), falling back to the model's global rate, instead of inheriting the rate of whatever drives it. That is a real difference from Simulink's block, which is a function of time rather than of sample count.
- Not linear, and so deliberately carries no state space. After the first sample the block is the identity, but on the first sample it is not, so no single A/B/C/D describes it – and a reduction that absorbed it would silently drop the initial value, which is the entire point of the block.
Code facts#
| Fact | Value |
|---|---|
| registered type | Control_Systems/Signal_Attributes/IC |
| family | Control_Systems/Signal_Attributes |
| solver environment class | ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_IC |
| source | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Attributes/IC/ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_IC.cpp |
| header | src/ICoreBlocks/ICoreBlockLibrary/Blocks/Control_Systems/Signal_Attributes/IC/ICoreBlock_0_Control_Systems_1_Signal_Attributes_2_IC.h |
| default size on canvas | 70 × 70 px |
| ports at insert | 1 in, 1 out |
| code generators implemented | Python, MATLAB, Java, Rust, C, C++, VHDL, Verilog, SystemVerilog, PLC Structured Text |
Ports#
| # | Direction | Signal type | Description label |
|---|---|---|---|
| 1 | in | ICoreDouble | — |
| 2 | out | ICoreDouble | — |
Ports the constructor creates. A block whose port list changes with its configuration adds or removes ports at load time; the count above is the one a freshly inserted block has.
Configuration variables#
| Config variable | Default | Simulink parameter |
|---|---|---|
Initial Value | 1 | Value |
Every block also carries Sampling Time (s) from ICoreBlockSolverEnvironment: zero or less inherits the solver's rate, a positive value runs the block at that period.
Simulink bridge#
| support | Support::Both |
| Simulink path | simulink/Signal Attributes/IC |
| port-count rule | PortsParam::None |
SampleTime parameter | yes |
| ICore config | Simulink parameter | Value translation |
|---|---|---|
Initial Value | Value | passes through |
Caveat (shown to the user): the block is discrete only on the ICore side: its state is a first-sample flag rather than a clock, so it takes its own "Sampling Time (s)" instead of inheriting the surrounding rate. Simulink's block is a function of time
Catalog contract: src/ICoreBlocks/ICoreCoder/ICoreCommandSystem/SimulinkBridge/ICoreSimulinkBlockCatalog.h
Description vs code#
The checker has a blind spot here — it could not resolve something (a grouped port bullet, a computed config name), which is reported and never counted as a pass. A reader has to settle it:
B0no sample under docs/generated/samples/ — nothing to cross-check (P8.1)
The verdict above is
tools/docs/check_block_descriptions.py(P7.1), which compares LISTS. It cannot read a sentence: "stateless" on a block with a state, an initial-value semantic the recursion does not implement, a "not synthesizable" caveat the HDL banner contradicts. That is the agent audit (P7.3) on BLOCK_DESCRIPTION_AUDIT.md, and this tool's green is not a substitute for one.
File banner (developer view)#
The top comment of the block's .cpp — the maths, the realization and the export strategy, addressed to whoever changes it. It must not contradict the description above (P7.5).
IC -- forces the signal's value on the first sample, then passes it through y[0] = Initial Value (every entry); y[k] = u[k] afterwards. See the header for the measured R2026a behaviour, for why the state is a FLAG rather than a value, and for why the block is discrete only.
Sample results#
No sample run is committed for this block. Samples come from the headless harness (DOCS_PLAN.md P8.1) into docs/generated/samples/; until one exists this block's behaviour is witnessed by the parity and export-verification suites, not by a plot here.